Add CXL DVSEC GPF time_scale 10s support

Ref CXL Spec chapter 8.1.6 and 8.1.7, Add time_scale 10s support.

When time_scale is 7h

Old code shows:
	GPF Phase 1 Timeout: 20<?>

New code shows
	GPF Phase 1 Timeout: 20s

The changes do not affect Reserved time scale encoding shows <?>.

Signed-off-by: yeeli <seven.yi.lee@gmail.com>

diff --git a/ls-ecaps.c b/ls-ecaps.c
index 0a7d906e4e3bae794a67ee3de3cf57ad68b4441a..6d652bcee5b40bf5ee9fb523c6a94ceaad6b48a4 100644 (file)
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -1052,7 +1052,7 @@ dvsec_cxl_gpf_device(struct device *d, int where)
   printf("\t\tGPF Phase 2 Duration: %u%s\n", duration,
       (time_scale < PCI_CXL_GPF_DEV_1MS) ? "us":
       (time_scale < PCI_CXL_GPF_DEV_1S) ? "ms" :
-      (time_scale == PCI_CXL_GPF_DEV_1S) ? "s" : "<?>");
+      (time_scale <= PCI_CXL_GPF_DEV_10S) ? "s" : "<?>");
 
   l = get_conf_long(d, where + PCI_CXL_GPF_DEV_PHASE2_POW);
   printf("\t\tGPF Phase 2 Power: %umW\n", (unsigned int)l);
@@ -1093,7 +1093,7 @@ dvsec_cxl_gpf_port(struct device *d, int where)
   printf("\t\tGPF Phase 1 Timeout: %d%s\n", timeout,
       (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us":
       (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" :
-      (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>");
+      (time_scale <= PCI_CXL_GPF_PORT_10S) ? "s" : "<?>");
 
   w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE2_CTRL);
   time_base = BITS(w, 0, 4);
@@ -1124,7 +1124,7 @@ dvsec_cxl_gpf_port(struct device *d, int where)
   printf("\t\tGPF Phase 2 Timeout: %d%s\n", timeout,
       (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us":
       (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" :
-      (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>");
+      (time_scale <= PCI_CXL_GPF_PORT_10S) ? "s" : "<?>");
 }
 
 static void