aarch64: Add support for FEAT_SSVE_BITPERM

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 11ee6c8af37ba7853faa3ec4d5b7f8f2a46f74f6..0ca54c3bd40bc87c8927c9e6f1ed1fb71e2ed289 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10834,7 +10834,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"sve2-sha3",                AARCH64_FEATURE (SVE2_SHA3),
                        AARCH64_FEATURES (2, SVE2, SHA3)},
   {"sve2-bitperm",     AARCH64_FEATURE (SVE2_BITPERM),
-                       AARCH64_FEATURE (SVE2)},
+                       AARCH64_FEATURES (2, SVE2, SVE_BITPERM)},
   {"sme",              AARCH64_FEATURE (SME),
                        AARCH64_FEATURES (3, BFLOAT16, F16, COMPNUM)},
   {"sme-f64",          AARCH64_FEATURE (SME_F64F64), AARCH64_FEATURE (SME)},
@@ -10870,7 +10870,11 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"f8f16mm",          AARCH64_FEATURE (F8F16MM), AARCH64_FEATURES (2, SIMD, FP8)},
   {"sve-aes",          AARCH64_FEATURE (SVE_AES), AARCH64_FEATURE (AES)},
   {"sve-aes2",         AARCH64_FEATURE (SVE_AES2), AARCH64_NO_FEATURES},
-  {"ssve-aes", AARCH64_FEATURE (SSVE_AES), AARCH64_FEATURES (2, SME2, SVE_AES)},
+  {"ssve-aes",         AARCH64_FEATURE (SSVE_AES),
+                       AARCH64_FEATURES (2, SME2, SVE_AES)},
+  {"sve-bitperm",      AARCH64_FEATURE (SVE_BITPERM), AARCH64_NO_FEATURES},
+  {"ssve-bitperm",     AARCH64_FEATURE (SSVE_BITPERM),
+                       AARCH64_FEATURES (2, SME2, SVE_BITPERM)},
   {"rcpc3",            AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
   {"cpa",              AARCH64_FEATURE (CPA), AARCH64_NO_FEATURES},
   {"faminmax",         AARCH64_FEATURE (FAMINMAX), AARCH64_FEATURE (SIMD)},

diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 39e1e8cd613efcd75f65b8b879d66ee533938fbf..9683d411ce9130af0bc7243b3991b92e028816e6 100644 (file)
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -323,6 +323,8 @@ automatically cause those extensions to be disabled.
  @tab Enable Speculative Store Bypassing Safe state read and write.
 @item @code{ssve-aes} @tab @code{sme2}, @code{sve-aes}
  @tab Enable SVE AES instructions in streaming mode.
+@item @code{ssve-bitperm} @tab @code{sme2}, @code{sve-bitperm}
+ @tab Enable SVE AES instructions in streaming mode.
 @item @code{ssve-fexpa} @tab @code{sme2}
  @tab Enable the SVE FEXPA instruction in streaming mode.
 @item @code{ssve-fp8dot2} @tab @code{sme2}, @code{fp8}
@@ -337,6 +339,8 @@ automatically cause those extensions to be disabled.
  @tab Enable the SVE2 AES and PMULL Extensions.
 @item @code{sve-aes2} @tab
 @tab Enable the SVE-AES2 extension.
+@item @code{sve-bitperm} @tab
+ @tab Enable the SVE2 BITPERM Extension.
 @item @code{sve-b16b16} @tab
 @tab Enable the SVE B16B16 extension.  These instructions also require either @code{+sve2} or @code{+sme2}.
 @item @code{sve-bfscale} @tab
@@ -347,7 +351,7 @@ automatically cause those extensions to be disabled.
  @tab Enable SVE2.
 @item @code{sve2-aes} @tab @code{sve2}, @code{sve-aes}
  @tab Enable the SVE2 AES and PMULL Extensions.
-@item @code{sve2-bitperm} @tab @code{sve2}
+@item @code{sve2-bitperm} @tab @code{sve2}, @code{sve-bitperm}
  @tab Enable the SVE2 BITPERM Extension.
 @item @code{sve2-sha3} @tab @code{sve2}, @code{sha3}
  @tab Enable the SVE2 SHA3 Extension.

diff --git a/gas/testsuite/gas/aarch64/sve-bitperm.d b/gas/testsuite/gas/aarch64/sve-bitperm.d
new file mode 100644 (file)
index 0000000..0f3be99
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-bitperm.d
@@ -0,0 +1,58 @@
+#as: -march=armv8-a+sve2+sve-bitperm
+#as: -march=armv8-a+ssve-bitperm
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+:   4500b400        bdep    z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:   4500b41f        bdep    z31\.b, z0\.b, z0\.b
+ *[0-9a-f]+:   4500b7e0        bdep    z0\.b, z31\.b, z0\.b
+ *[0-9a-f]+:   451fb400        bdep    z0\.b, z0\.b, z31\.b
+ *[0-9a-f]+:   4540b400        bdep    z0\.h, z0\.h, z0\.h
+ *[0-9a-f]+:   4540b41f        bdep    z31\.h, z0\.h, z0\.h
+ *[0-9a-f]+:   4540b7e0        bdep    z0\.h, z31\.h, z0\.h
+ *[0-9a-f]+:   455fb400        bdep    z0\.h, z0\.h, z31\.h
+ *[0-9a-f]+:   4580b400        bdep    z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:   4580b41f        bdep    z31\.s, z0\.s, z0\.s
+ *[0-9a-f]+:   4580b7e0        bdep    z0\.s, z31\.s, z0\.s
+ *[0-9a-f]+:   459fb400        bdep    z0\.s, z0\.s, z31\.s
+ *[0-9a-f]+:   45c0b400        bdep    z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:   45c0b41f        bdep    z31\.d, z0\.d, z0\.d
+ *[0-9a-f]+:   45c0b7e0        bdep    z0\.d, z31\.d, z0\.d
+ *[0-9a-f]+:   45dfb400        bdep    z0\.d, z0\.d, z31\.d
+ *[0-9a-f]+:   4500b000        bext    z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:   4500b01f        bext    z31\.b, z0\.b, z0\.b
+ *[0-9a-f]+:   4500b3e0        bext    z0\.b, z31\.b, z0\.b
+ *[0-9a-f]+:   451fb000        bext    z0\.b, z0\.b, z31\.b
+ *[0-9a-f]+:   4540b000        bext    z0\.h, z0\.h, z0\.h
+ *[0-9a-f]+:   4540b01f        bext    z31\.h, z0\.h, z0\.h
+ *[0-9a-f]+:   4540b3e0        bext    z0\.h, z31\.h, z0\.h
+ *[0-9a-f]+:   455fb000        bext    z0\.h, z0\.h, z31\.h
+ *[0-9a-f]+:   4580b000        bext    z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:   4580b01f        bext    z31\.s, z0\.s, z0\.s
+ *[0-9a-f]+:   4580b3e0        bext    z0\.s, z31\.s, z0\.s
+ *[0-9a-f]+:   459fb000        bext    z0\.s, z0\.s, z31\.s
+ *[0-9a-f]+:   45c0b000        bext    z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:   45c0b01f        bext    z31\.d, z0\.d, z0\.d
+ *[0-9a-f]+:   45c0b3e0        bext    z0\.d, z31\.d, z0\.d
+ *[0-9a-f]+:   45dfb000        bext    z0\.d, z0\.d, z31\.d
+ *[0-9a-f]+:   4500b800        bgrp    z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:   4500b81f        bgrp    z31\.b, z0\.b, z0\.b
+ *[0-9a-f]+:   4500bbe0        bgrp    z0\.b, z31\.b, z0\.b
+ *[0-9a-f]+:   451fb800        bgrp    z0\.b, z0\.b, z31\.b
+ *[0-9a-f]+:   4540b800        bgrp    z0\.h, z0\.h, z0\.h
+ *[0-9a-f]+:   4540b81f        bgrp    z31\.h, z0\.h, z0\.h
+ *[0-9a-f]+:   4540bbe0        bgrp    z0\.h, z31\.h, z0\.h
+ *[0-9a-f]+:   455fb800        bgrp    z0\.h, z0\.h, z31\.h
+ *[0-9a-f]+:   4580b800        bgrp    z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:   4580b81f        bgrp    z31\.s, z0\.s, z0\.s
+ *[0-9a-f]+:   4580bbe0        bgrp    z0\.s, z31\.s, z0\.s
+ *[0-9a-f]+:   459fb800        bgrp    z0\.s, z0\.s, z31\.s
+ *[0-9a-f]+:   45c0b800        bgrp    z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:   45c0b81f        bgrp    z31\.d, z0\.d, z0\.d
+ *[0-9a-f]+:   45c0bbe0        bgrp    z0\.d, z31\.d, z0\.d
+ *[0-9a-f]+:   45dfb800        bgrp    z0\.d, z0\.d, z31\.d

diff --git a/gas/testsuite/gas/aarch64/sve-bitperm.s b/gas/testsuite/gas/aarch64/sve-bitperm.s
new file mode 100644 (file)
index 0000000..5cfae1a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-bitperm.s
@@ -0,0 +1,48 @@
+       bdep    z0.b, z0.b, z0.b
+       bdep    z31.b, z0.b, z0.b
+       bdep    z0.b, z31.b, z0.b
+       bdep    z0.b, z0.b, z31.b
+       bdep    z0.h, z0.h, z0.h
+       bdep    z31.h, z0.h, z0.h
+       bdep    z0.h, z31.h, z0.h
+       bdep    z0.h, z0.h, z31.h
+       bdep    z0.s, z0.s, z0.s
+       bdep    z31.s, z0.s, z0.s
+       bdep    z0.s, z31.s, z0.s
+       bdep    z0.s, z0.s, z31.s
+       bdep    z0.d, z0.d, z0.d
+       bdep    z31.d, z0.d, z0.d
+       bdep    z0.d, z31.d, z0.d
+       bdep    z0.d, z0.d, z31.d
+       bext    z0.b, z0.b, z0.b
+       bext    z31.b, z0.b, z0.b
+       bext    z0.b, z31.b, z0.b
+       bext    z0.b, z0.b, z31.b
+       bext    z0.h, z0.h, z0.h
+       bext    z31.h, z0.h, z0.h
+       bext    z0.h, z31.h, z0.h
+       bext    z0.h, z0.h, z31.h
+       bext    z0.s, z0.s, z0.s
+       bext    z31.s, z0.s, z0.s
+       bext    z0.s, z31.s, z0.s
+       bext    z0.s, z0.s, z31.s
+       bext    z0.d, z0.d, z0.d
+       bext    z31.d, z0.d, z0.d
+       bext    z0.d, z31.d, z0.d
+       bext    z0.d, z0.d, z31.d
+       bgrp    z0.b, z0.b, z0.b
+       bgrp    z31.b, z0.b, z0.b
+       bgrp    z0.b, z31.b, z0.b
+       bgrp    z0.b, z0.b, z31.b
+       bgrp    z0.h, z0.h, z0.h
+       bgrp    z31.h, z0.h, z0.h
+       bgrp    z0.h, z31.h, z0.h
+       bgrp    z0.h, z0.h, z31.h
+       bgrp    z0.s, z0.s, z0.s
+       bgrp    z31.s, z0.s, z0.s
+       bgrp    z0.s, z31.s, z0.s
+       bgrp    z0.s, z0.s, z31.s
+       bgrp    z0.d, z0.d, z0.d
+       bgrp    z31.d, z0.d, z0.d
+       bgrp    z0.d, z31.d, z0.d
+       bgrp    z0.d, z0.d, z31.d

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 5af991adb9b8cea20768eb332e27e7a1d51cb56c..e65b61c3f9c2a82043248e75807f5e3326ca2f26 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -205,6 +205,10 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_SVE_AES2,
   /* SSVE_AES extension. */
   AARCH64_FEATURE_SSVE_AES,
+  /* SVE_BITPERM extension. */
+  AARCH64_FEATURE_SVE_BITPERM,
+  /* SSVE_BITPERM extension. */
+  AARCH64_FEATURE_SSVE_BITPERM,
   /* RCPC3 instructions.  */
   AARCH64_FEATURE_RCPC3,
   /* Checked Pointer Arithmetic instructions. */

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 90d79660e7a4b8711dead7159b0479b1d451c19e..e7b17061d827fa2be2f8a6ce2471d13fed986c9c 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2892,7 +2892,7 @@ static const aarch64_feature_set aarch64_feature_sve2sha3 =
 static const aarch64_feature_set aarch64_feature_sve2sm4 =
   AARCH64_FEATURE (SVE2_SM4);
 static const aarch64_feature_set aarch64_feature_sve2bitperm =
-  AARCH64_FEATURE (SVE2_BITPERM);
+  AARCH64_FEATURE (SVE_BITPERM);
 static const aarch64_feature_set aarch64_feature_sme =
   AARCH64_FEATURE (SME);
 static const aarch64_feature_set aarch64_feature_sme_f64f64 =