+++ /dev/null
-From d2c595840ed4c36751bfcfea73e21f6e390e165d Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 28 Jul 2022 13:37:47 +0200
-Subject: arm64: dts: qcom: sdm845: narrow LLCC address space
-
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-
-[ Upstream commit 300b5f661eebefb8571841b78091343eb87eca54 ]
-
-The Last Level Cache Controller (LLCC) device does not need to access
-entire LLCC address space. Currently driver uses only hardware info and
-status registers which both reside in LLCC0_COMMON range (offset
-0x30000, size 0x1000). Narrow the address space to allow binding other
-drivers to rest of LLCC address space.
-
-Cc: Rajendra Nayak <quic_rjendra@quicinc.com>
-Cc: Sibi Sankar <quic_sibis@quicinc.com>
-Reported-by: Steev Klimaszewski <steev@kali.org>
-Suggested-by: Sibi Sankar <quic_sibis@quicinc.com>
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Tested-by: Steev Klimaszewski <steev@kali.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220728113748.170548-11-krzysztof.kozlowski@linaro.org
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
-index 9beb3c34fcdb..068fad00e615 100644
---- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
-+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
-@@ -1796,7 +1796,7 @@
-
- system-cache-controller@1100000 {
- compatible = "qcom,sdm845-llcc";
-- reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
-+ reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>;
- reg-names = "llcc_base", "llcc_broadcast_base";
- interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
- };
---
-2.35.1
-
mmc-sdhci-msm-add-compatible-string-check-for-sdm670.patch
drm-dp-don-t-rewrite-link-config-when-setting-phy-te.patch
drm-amd-display-remove-interface-for-periodic-interr.patch
-arm64-dts-qcom-sdm845-narrow-llcc-address-space.patch
arm-dts-imx7d-sdb-config-the-max-pressure-for-tsc204.patch
arm-dts-imx6q-add-missing-properties-for-sram.patch
arm-dts-imx6dl-add-missing-properties-for-sram.patch
+++ /dev/null
-From b06496f6e669d25307e4015cecd8b2d40cf47341 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 28 Jul 2022 13:37:47 +0200
-Subject: arm64: dts: qcom: sdm845: narrow LLCC address space
-
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-
-[ Upstream commit 300b5f661eebefb8571841b78091343eb87eca54 ]
-
-The Last Level Cache Controller (LLCC) device does not need to access
-entire LLCC address space. Currently driver uses only hardware info and
-status registers which both reside in LLCC0_COMMON range (offset
-0x30000, size 0x1000). Narrow the address space to allow binding other
-drivers to rest of LLCC address space.
-
-Cc: Rajendra Nayak <quic_rjendra@quicinc.com>
-Cc: Sibi Sankar <quic_sibis@quicinc.com>
-Reported-by: Steev Klimaszewski <steev@kali.org>
-Suggested-by: Sibi Sankar <quic_sibis@quicinc.com>
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Tested-by: Steev Klimaszewski <steev@kali.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220728113748.170548-11-krzysztof.kozlowski@linaro.org
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
-index ea7a272d267a..ce523ec8dd28 100644
---- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
-+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
-@@ -1968,7 +1968,7 @@
-
- system-cache-controller@1100000 {
- compatible = "qcom,sdm845-llcc";
-- reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
-+ reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>;
- reg-names = "llcc_base", "llcc_broadcast_base";
- interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
- };
---
-2.35.1
-
mmc-sdhci-msm-add-compatible-string-check-for-sdm670.patch
drm-dp-don-t-rewrite-link-config-when-setting-phy-te.patch
drm-amd-display-remove-interface-for-periodic-interr.patch
-arm64-dts-qcom-sdm845-narrow-llcc-address-space.patch
arm-dts-imx7d-sdb-config-the-max-pressure-for-tsc204.patch
arm64-dts-qcom-sc7280-idp-correct-adc-channel-node-n.patch
arm-dts-imx6q-add-missing-properties-for-sram.patch
+++ /dev/null
-From 0a956cf8c57b1139c024bdc1e94859819410e9a8 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 28 Jul 2022 13:37:47 +0200
-Subject: arm64: dts: qcom: sdm845: narrow LLCC address space
-
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-
-[ Upstream commit 300b5f661eebefb8571841b78091343eb87eca54 ]
-
-The Last Level Cache Controller (LLCC) device does not need to access
-entire LLCC address space. Currently driver uses only hardware info and
-status registers which both reside in LLCC0_COMMON range (offset
-0x30000, size 0x1000). Narrow the address space to allow binding other
-drivers to rest of LLCC address space.
-
-Cc: Rajendra Nayak <quic_rjendra@quicinc.com>
-Cc: Sibi Sankar <quic_sibis@quicinc.com>
-Reported-by: Steev Klimaszewski <steev@kali.org>
-Suggested-by: Sibi Sankar <quic_sibis@quicinc.com>
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Tested-by: Steev Klimaszewski <steev@kali.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220728113748.170548-11-krzysztof.kozlowski@linaro.org
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
-index 7783005c8028..6d9787e32b88 100644
---- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
-+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
-@@ -2021,7 +2021,7 @@
-
- llcc: system-cache-controller@1100000 {
- compatible = "qcom,sdm845-llcc";
-- reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
-+ reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>;
- reg-names = "llcc_base", "llcc_broadcast_base";
- interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
- };
---
-2.35.1
-
drm-amd-display-remove-interface-for-periodic-interr.patch
drm-amd-display-polling-vid-stream-status-in-hpo-dp-.patch
drm-amdkfd-fix-ubsan-shift-out-of-bounds-warning.patch
-arm64-dts-qcom-sdm845-narrow-llcc-address-space.patch
arm-dts-imx6-delete-interrupts-property-if-interrupt.patch
arm-dts-imx7d-sdb-config-the-max-pressure-for-tsc204.patch
arm64-dts-qcom-sc7280-idp-correct-adc-channel-node-n.patch
+++ /dev/null
-From d27b2d0c7a068be1e6a3d804b213a0593df0d7ef Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 28 Jul 2022 13:37:47 +0200
-Subject: arm64: dts: qcom: sdm845: narrow LLCC address space
-
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-
-[ Upstream commit 300b5f661eebefb8571841b78091343eb87eca54 ]
-
-The Last Level Cache Controller (LLCC) device does not need to access
-entire LLCC address space. Currently driver uses only hardware info and
-status registers which both reside in LLCC0_COMMON range (offset
-0x30000, size 0x1000). Narrow the address space to allow binding other
-drivers to rest of LLCC address space.
-
-Cc: Rajendra Nayak <quic_rjendra@quicinc.com>
-Cc: Sibi Sankar <quic_sibis@quicinc.com>
-Reported-by: Steev Klimaszewski <steev@kali.org>
-Suggested-by: Sibi Sankar <quic_sibis@quicinc.com>
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Tested-by: Steev Klimaszewski <steev@kali.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220728113748.170548-11-krzysztof.kozlowski@linaro.org
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
-index 2287354fef86..76f905c32aee 100644
---- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
-+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
-@@ -1359,7 +1359,7 @@
-
- cache-controller@1100000 {
- compatible = "qcom,sdm845-llcc";
-- reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
-+ reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>;
- reg-names = "llcc_base", "llcc_broadcast_base";
- interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
- };
---
-2.35.1
-
platform-x86-msi-laptop-change-dmi-match-alias-strin.patch
drm-amdgpu-fix-initial-connector-audio-value.patch
mmc-sdhci-msm-add-compatible-string-check-for-sdm670.patch
-arm64-dts-qcom-sdm845-narrow-llcc-address-space.patch
arm-dts-imx7d-sdb-config-the-max-pressure-for-tsc204.patch
arm-dts-imx6q-add-missing-properties-for-sram.patch
arm-dts-imx6dl-add-missing-properties-for-sram.patch
+++ /dev/null
-From b2c83d7350882592f9c9be9a163fc5a60704ab00 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 28 Jul 2022 13:37:47 +0200
-Subject: arm64: dts: qcom: sdm845: narrow LLCC address space
-
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-
-[ Upstream commit 300b5f661eebefb8571841b78091343eb87eca54 ]
-
-The Last Level Cache Controller (LLCC) device does not need to access
-entire LLCC address space. Currently driver uses only hardware info and
-status registers which both reside in LLCC0_COMMON range (offset
-0x30000, size 0x1000). Narrow the address space to allow binding other
-drivers to rest of LLCC address space.
-
-Cc: Rajendra Nayak <quic_rjendra@quicinc.com>
-Cc: Sibi Sankar <quic_sibis@quicinc.com>
-Reported-by: Steev Klimaszewski <steev@kali.org>
-Suggested-by: Sibi Sankar <quic_sibis@quicinc.com>
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Tested-by: Steev Klimaszewski <steev@kali.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220728113748.170548-11-krzysztof.kozlowski@linaro.org
-Stable-dep-of: 5a0504945878 ("arm64: dts: qcom: sdm845-xiaomi-polaris: Fix sde_dsi_active pinctrl")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
-index f0e286715d1b..4d5ae5897d1d 100644
---- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
-+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
-@@ -2138,7 +2138,7 @@
-
- llcc: system-cache-controller@1100000 {
- compatible = "qcom,sdm845-llcc";
-- reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
-+ reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>;
- reg-names = "llcc_base", "llcc_broadcast_base";
- interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
- };
---
-2.35.1
-
arm64-dts-renesas-r9a07g054-fix-sci-rx-tx-interrupt-.patch
arm64-dts-renesas-r9a07g043-fix-sci-rx-tx-interrupt-.patch
dt-bindings-clock-exynosautov9-correct-clock-numberi.patch
-arm64-dts-qcom-sdm845-narrow-llcc-address-space.patch
arm64-dts-qcom-sdm845-xiaomi-polaris-fix-sde_dsi_act.patch
arm64-dts-qcom-sc7280-cleanup-the-lpasscc-node.patch
arm64-dts-qcom-sc7280-update-lpasscore-node.patch