arm64: zynqmp: Fix binding of hclk clock (gem nodes)

This patch is required to fix binding of gem interface clocks to
system-level clock IDs that have changed. The gem0 clock IDs are now:
1) Clock ID 45 represents GEM0_TX clock
2) Clock ID 49 represents GEM0_RX clock
3) Clock ID 104 represents GEM0_REF clock

Clock IDs for other gems changed similarly, e.g. for i in {1, 2, 3}
GEMi_TX = GEM0_TX + i, etc. Other clock IDs have not changed.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <willw@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index bfa2612c302eae47f71728e79ff583ca3c890840..6b2702b4daf2f8eb564f1d01bba88b5a14c82bff 100644 (file)
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -168,22 +168,22 @@
 };
 
 &gem0 {
-       clocks = <&clk 31>, <&clk 49>, <&clk 45>, <&clk 49>, <&clk 44>;
+       clocks = <&clk 31>, <&clk 104>, <&clk 45>, <&clk 49>, <&clk 44>;
        clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };
 
 &gem1 {
-       clocks = <&clk 31>, <&clk 50>, <&clk 46>, <&clk 50>, <&clk 44>;
+       clocks = <&clk 31>, <&clk 105>, <&clk 46>, <&clk 50>, <&clk 44>;
        clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };
 
 &gem2 {
-       clocks = <&clk 31>, <&clk 51>, <&clk 47>, <&clk 51>, <&clk 44>;
+       clocks = <&clk 31>, <&clk 106>, <&clk 47>, <&clk 51>, <&clk 44>;
        clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };
 
 &gem3 {
-       clocks = <&clk 31>, <&clk 52>, <&clk 48>, <&clk 52>, <&clk 44>;
+       clocks = <&clk 31>, <&clk 107>, <&clk 48>, <&clk 52>, <&clk 44>;
        clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };