Add -Werror to the build flags for amdgpu.ko.
Only enable this if you are warning code for amdgpu.ko.
-config DRM_AMDGPU_NAVI3X_USERQ
- bool "Enable amdgpu usermode queues"
- depends on DRM_AMDGPU
- default n
- help
- Choose this option to enable GFX usermode queue support for GFX/SDMA/Compute
- workload submission. This feature is experimental and supported on GFX11+.
-
source "drivers/gpu/drm/amd/acp/Kconfig"
source "drivers/gpu/drm/amd/display/Kconfig"
source "drivers/gpu/drm/amd/amdkfd/Kconfig"
mes_v12_0.o \
# add GFX userqueue support
-amdgpu-$(CONFIG_DRM_AMDGPU_NAVI3X_USERQ) += mes_userqueue.o
+amdgpu-y += mes_userqueue.o
# add UVD block
amdgpu-y += \
amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
amdgpu_amdkfd_suspend(adev, false);
-#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
amdgpu_userq_suspend(adev);
-#endif
/* Workaround for ASICs need to disable SMC first */
amdgpu_device_smu_fini_early(adev);
if (!adev->in_s0ix) {
amdgpu_amdkfd_suspend(adev, adev->in_runpm);
-#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
amdgpu_userq_suspend(adev);
-#endif
}
r = amdgpu_device_evict_resources(adev);
r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
if (r)
goto exit;
-#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
+
r = amdgpu_userq_resume(adev);
if (r)
goto exit;
-#endif
}
r = amdgpu_device_ip_late_init(adev);
if (adev->gfx.userq_sch_req_count[idx] == 0) {
cancel_delayed_work_sync(&adev->gfx.enforce_isolation[idx].work);
if (!adev->gfx.userq_sch_inactive[idx]) {
-#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
amdgpu_userq_stop_sched_for_enforce_isolation(adev, idx);
-#endif
if (adev->kfd.init_complete)
amdgpu_amdkfd_stop_sched(adev, idx);
adev->gfx.userq_sch_inactive[idx] = true;
/* Tell KFD to resume the runqueue */
WARN_ON_ONCE(!adev->gfx.userq_sch_inactive[idx]);
WARN_ON_ONCE(adev->gfx.userq_sch_req_count[idx]);
-#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
+
amdgpu_userq_start_sched_for_enforce_isolation(adev, idx);
-#endif
if (adev->kfd.init_complete)
amdgpu_amdkfd_start_sched(adev, idx);
adev->gfx.userq_sch_inactive[idx] = false;
return ret;
}
-#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
static struct amdgpu_usermode_queue *
amdgpu_userq_find(struct amdgpu_userq_mgr *uq_mgr, int qid)
{
return r;
}
-#else
-int amdgpu_userq_ioctl(struct drm_device *dev, void *data,
- struct drm_file *filp)
-{
- return -ENOTSUPP;
-}
-#endif
static int
amdgpu_userq_restore_all(struct amdgpu_userq_mgr *uq_mgr)
kref_put(&fence_drv->refcount, amdgpu_userq_fence_driver_destroy);
}
-#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
static int amdgpu_userq_fence_alloc(struct amdgpu_userq_fence **userq_fence)
{
*userq_fence = kmem_cache_alloc(amdgpu_userq_fence_slab, GFP_ATOMIC);
return 0;
}
-#endif
static const char *amdgpu_userq_fence_get_driver_name(struct dma_fence *f)
{
.release = amdgpu_userq_fence_release,
};
-#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
/**
* amdgpu_userq_fence_read_wptr - Read the userq wptr value
*
return r;
}
-#else
-int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data,
- struct drm_file *filp)
-{
- return -ENOTSUPP;
-}
-#endif
-#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
{
return r;
}
-#else
-int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data,
- struct drm_file *filp)
-{
- return -ENOTSUPP;
-}
-#endif
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 2):
case IP_VERSION(11, 0, 3):
-#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
if (!adev->gfx.disable_uq &&
adev->gfx.me_fw_version >= 2390 &&
adev->gfx.pfp_fw_version >= 2530 &&
adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
}
-#endif
break;
case IP_VERSION(11, 0, 1):
case IP_VERSION(11, 0, 4):
case IP_VERSION(11, 5, 1):
case IP_VERSION(11, 5, 2):
case IP_VERSION(11, 5, 3):
-#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
/* add firmware version checks here */
if (0 && !adev->gfx.disable_uq) {
adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
}
-#endif
break;
default:
break;
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
case IP_VERSION(12, 0, 0):
case IP_VERSION(12, 0, 1):
-#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
if (!adev->gfx.disable_uq &&
adev->gfx.me_fw_version >= 2780 &&
adev->gfx.pfp_fw_version >= 2840 &&
adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
}
-#endif
break;
default:
break;
else
DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
-#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
/* add firmware version checks here */
if (0 && !adev->sdma.disable_uq)
adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
-#endif
+
r = amdgpu_sdma_sysfs_reset_mask_init(adev);
if (r)
return r;
else
DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
-#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
/* add firmware version checks here */
if (0 && !adev->sdma.disable_uq)
adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
-#endif
-
return r;
}