RISC-V: Support ssqosid extension with version 1.0.

It only add one new CSR: `srmcfg`.

Ref: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index c9e4b03b17daa96bf06d36096abe22fd757106a3..fd2cb74df8081f147a880a884a3ef2c0ccb29fcf 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1476,6 +1476,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
   {"svinval",          ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"svnapot",          ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"svpbmt",           ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
+  {"ssqosid",          ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {NULL, 0, 0, 0, 0}
 };
 

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index ca269bd9a46a062da31fdebe554fe418ba95a1b1..bd8b020ca49029f640c494887c721ea8a0432a21 100644 (file)
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -105,6 +105,7 @@ enum riscv_csr_class
   CSR_CLASS_SSTC_32,           /* Sstc RV32 only */
   CSR_CLASS_SSTC_AND_H_32,     /* Sstc RV32 only (with H) */
   CSR_CLASS_SSCTR,             /* Ssctr */
+  CSR_CLASS_SSQOSID,           /* Ssqosid */
   CSR_CLASS_XTHEADVECTOR,      /* xtheadvector only */
 };
 
@@ -1166,6 +1167,9 @@ riscv_csr_address (const char *csr_name,
     case CSR_CLASS_XTHEADVECTOR:
       extension = "xtheadvector";
       break;
+    case CSR_CLASS_SSQOSID:
+      extension = "ssqosid";
+      break;
     default:
       as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
     }

diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
index 07297954c517f7fd6dd104dfe0709c98cc4da5a5..6896e7b1ccdb04e2d9b1f930c7d3a8c463ce2928 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p10.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
@@ -933,3 +933,5 @@ Disassembly of section .text:
 [      ]+[0-9a-f]+:[   ]+c2259073[     ]+csrw[         ]+vlenb,a1
 [      ]+[0-9a-f]+:[   ]+01702573[     ]+csrr[         ]+a0,jvt
 [      ]+[0-9a-f]+:[   ]+01759073[     ]+csrw[         ]+jvt,a1
+[      ]+[0-9a-f]+:[   ]+18102573[     ]+csrr[         ]+a0,srmcfg
+[      ]+[0-9a-f]+:[   ]+18159073[     ]+csrw[         ]+srmcfg,a1

diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l
index 2427ba98ecc6a866efe143ca8cae0204bbfd4d6c..46d1e4e5849d5fd64aa1575c5727de3a1e549361 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p10.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.l
@@ -1717,3 +1717,7 @@
 .*Info: macro .*
 .*Warning: invalid CSR `jvt', needs `zcmt' extension
 .*Info: macro .*
+.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension
+.*Info: macro .*
+.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension
+.*Info: macro .*

diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
index 70cafb8812eeb0c8c86ee76e213fab3aff27aecb..308140aa064a6ff7dba0860797b0b99cf0d19ca9 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p11.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
@@ -933,3 +933,5 @@ Disassembly of section .text:
 [      ]+[0-9a-f]+:[   ]+c2259073[     ]+csrw[         ]+vlenb,a1
 [      ]+[0-9a-f]+:[   ]+01702573[     ]+csrr[         ]+a0,jvt
 [      ]+[0-9a-f]+:[   ]+01759073[     ]+csrw[         ]+jvt,a1
+[      ]+[0-9a-f]+:[   ]+18102573[     ]+csrr[         ]+a0,srmcfg
+[      ]+[0-9a-f]+:[   ]+18159073[     ]+csrw[         ]+srmcfg,a1

diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l
index aeec089288da51019891d3d1df03e801badbf8b6..9e813e206cdc3e657de9429f8d52541ab59194d9 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p11.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.l
@@ -1713,3 +1713,7 @@
 .*Info: macro .*
 .*Warning: invalid CSR `jvt', needs `zcmt' extension
 .*Info: macro .*
+.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension
+.*Info: macro .*
+.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension
+.*Info: macro .*

diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
index daf79f486ffdd74c5f286a2ae932bad8d544c646..5fe33162c9c34976e60402c7676516e55123b141 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p12.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
@@ -933,3 +933,5 @@ Disassembly of section .text:
 [      ]+[0-9a-f]+:[   ]+c2259073[     ]+csrw[         ]+vlenb,a1
 [      ]+[0-9a-f]+:[   ]+01702573[     ]+csrr[         ]+a0,jvt
 [      ]+[0-9a-f]+:[   ]+01759073[     ]+csrw[         ]+jvt,a1
+[      ]+[0-9a-f]+:[   ]+18102573[     ]+csrr[         ]+a0,srmcfg
+[      ]+[0-9a-f]+:[   ]+18159073[     ]+csrw[         ]+srmcfg,a1

diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l
index 3710da9f0806b6ff9d92177425916807665aea34..ff60ec0076711e25f67c9fd699de141902a8fa26 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p12.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.l
@@ -1477,3 +1477,7 @@
 .*Info: macro .*
 .*Warning: invalid CSR `jvt', needs `zcmt' extension
 .*Info: macro .*
+.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension
+.*Info: macro .*
+.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension
+.*Info: macro .*

diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s
index 44fc1e72809d3219d2ad5b32266462dca980c68e..6244bd73481dffc0fb895a71383d1afdfcffbf1f 100644 (file)
--- a/gas/testsuite/gas/riscv/csr.s
+++ b/gas/testsuite/gas/riscv/csr.s
@@ -541,3 +541,6 @@
 
        # Zcmt
        csr jvt
+
+       # Ssqosid
+       csr srmcfg

diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index f92c98fc4c5e478089478d14ec2d6830abe90c50..b7975ff9ade2627bc712e71a18bdce5ab3423212 100644 (file)
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -139,6 +139,7 @@ All available -march extensions for RISC-V:
        svinval                                 1.0
        svnapot                                 1.0
        svpbmt                                  1.0
+       ssqosid                                 1.0
        xcvalu                                  1.0
        xcvbi                                   1.0
        xcvbitmanip                             1.0

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 71ad7fff84d657c255aac697e44670022ff9c3c7..24af3ac531b78041d05f465b7cc00a824f7e32d4 100644 (file)
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -4254,6 +4254,8 @@
 #define CSR_VL 0xc20
 #define CSR_VTYPE 0xc21
 #define CSR_VLENB 0xc22
+/* Ssqosid CSR addresses.  */
+#define CSR_SRMCFG 0x181
 #endif /* RISCV_ENCODING_H */
 #ifdef DECLARE_INSN
 DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
@@ -5393,6 +5395,8 @@ DECLARE_CSR(vcsr, CSR_VCSR, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_N
 DECLARE_CSR(vl, CSR_VL, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(vtype, CSR_VTYPE, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(vlenb, CSR_VLENB, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+/* Ssqosid CSR.  */
+DECLARE_CSR(srmcfg, CSR_SRMCFG, CSR_CLASS_SSQOSID, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 #endif /* DECLARE_CSR */
 #ifdef DECLARE_CSR_ALIAS
 DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)