MAINTAINERS: degrade RISC-V MISC SOC SUPPORT to Odd Fixes

The SiFive and Canaan platforms are not being actively looked after at
this point, but fixes for them would be applied if/when the patches
appeared. Since they're now the only things in the RISC-V MISC SOC
SUPPORT, mark them as Odd Fixes. I don't believe this is a functional
change, it just represents what's actually happening - particularly
since the Canaan k230 never built up enough steam to get merged and the
new SiFive demo chips have been done in partnership with with other
companies, e.g. Eswin, and will reside in their directories instead.

Reviewed-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/MAINTAINERS b/MAINTAINERS
index 4981224985b4f41a646361ed42eee2254ae9fe89..72bfa33aa225d48a751af9de7e3d4811e1ba610e 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22115,7 +22115,7 @@ F:      include/soc/microchip/mpfs.h
 RISC-V MISC SOC SUPPORT
 M:     Conor Dooley <conor@kernel.org>
 L:     linux-riscv@lists.infradead.org
-S:     Maintained
+S:     Odd Fixes
 T:     git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
 F:     arch/riscv/boot/dts/canaan/
 F:     arch/riscv/boot/dts/sifive/