RISC-V: Remove incorrect earliest vsetvl post optimization[PR111313]

This patch removes the incorrect earliest poset vsetvl optimization,
such bug was found in vect-double-reduc-5.c which is runtime(execution fail) and also in PR111313.

For VLMAX intrinsics, we always emit a bogus patter which is vlmax_avl (see vector.md) to
occupy a scalar register which is used by the following RVV instruction which is VLMAX AVL.

Then for O2, O3, Ofast, earliest LCM works so well.
However, for O1, the vlmax_avl is not well optimized in the before pass which confused LCM earliest
so that we will end up with some redundant vsetvli zero,zero instructions in O1. (Note that O2 O3 Ofast are all good).

To elide those redundant vsetvli zero,zero, I added cleanup_earliest_vsetvls to elide those redundant vsetvls.

Now, after I review the implementation of this post optimizaiton again, I found it is incorrect and it is hard to
do the post optimizations for vsetvls that earliest LCM failed to eliminate.

Besides, such performance issues only happen in O1 or O0, such issues may not be serious.
So remove it and we may will find another way (E.g. adjust vlmax_avl pattern COST)
to optimize it if we really need to care about performance for O1.

	PR target/111313

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc (pass_vsetvl::cleanup_earliest_vsetvls): Remove.
	(pass_vsetvl::df_post_optimization): Remove incorrect function.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/vsetvl/avl_single-13.c: Adapt test.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c: Skip check for O1.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/pr111313.c: New test.

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index dd9aeb32b5639845e33ed83abf208fc93c3d057b..ae362a3f6a8c4f0785d564da4f905cd733b19925 100644 (file)
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -2846,7 +2846,6 @@ private:
   void ssa_post_optimization (void) const;
 
   /* Phase 6.  */
-  bool cleanup_earliest_vsetvls (const basic_block) const;
   void df_post_optimization (void) const;
 
   void init (void);
@@ -4183,61 +4182,6 @@ has_no_uses (basic_block cfg_bb, rtx_insn *rinsn, int regno)
   return true;
 }
 
-/* For many reasons, we failed to elide the redundant vsetvls
-   in Phase 3 and Phase 4.
-
-     - VLMAX-AVL case: 'vlmax_avl<mode>' may locate at some unlucky
-       point which make us set ANTLOC as false for LCM in 'O1'.
-       We don't want to complicate phase 3 and phase 4 too much,
-       so we do the post optimization for redundant VSETVLs here.
-*/
-bool
-pass_vsetvl::cleanup_earliest_vsetvls (const basic_block cfg_bb) const
-{
-  bool is_earliest_p = false;
-  if (cfg_bb->index >= (int) m_vector_manager->vector_block_infos.length ())
-    is_earliest_p = true;
-
-  rtx_insn *rinsn
-    = get_first_vsetvl_before_rvv_insns (cfg_bb, VSETVL_VTYPE_CHANGE_ONLY);
-  if (!rinsn)
-    return is_earliest_p;
-
-  sbitmap avail;
-  if (is_earliest_p)
-    {
-      gcc_assert (single_succ_p (cfg_bb) && single_pred_p (cfg_bb));
-      const bb_info *pred_bb = crtl->ssa->bb (single_pred (cfg_bb));
-      gcc_assert (pred_bb->index ()
-                 < m_vector_manager->vector_block_infos.length ());
-      avail = m_vector_manager->vector_avout[pred_bb->index ()];
-    }
-  else
-    avail = m_vector_manager->vector_avin[cfg_bb->index];
-
-  if (!bitmap_empty_p (avail))
-    {
-      unsigned int bb_index;
-      sbitmap_iterator sbi;
-      vector_insn_info strictest_info = vector_insn_info ();
-      EXECUTE_IF_SET_IN_BITMAP (avail, 0, bb_index, sbi)
-       {
-         const auto *expr = m_vector_manager->vector_exprs[bb_index];
-         if (strictest_info.uninit_p ()
-             || !expr->compatible_p (
-               static_cast<const vl_vtype_info &> (strictest_info)))
-           strictest_info = *expr;
-       }
-      vector_insn_info info;
-      info.parse_insn (rinsn);
-      if (!strictest_info.same_vtype_p (info))
-       return is_earliest_p;
-      eliminate_insn (rinsn);
-    }
-
-  return is_earliest_p;
-}
-
 /* This function does the following post optimization base on dataflow
    analysis:
 
@@ -4257,8 +4201,6 @@ pass_vsetvl::df_post_optimization (void) const
   rtx_insn *rinsn;
   FOR_ALL_BB_FN (cfg_bb, cfun)
     {
-      if (cleanup_earliest_vsetvls (cfg_bb))
-       continue;
       FOR_BB_INSNS (cfg_bb, rinsn)
        {
          if (NONDEBUG_INSN_P (rinsn) && vsetvl_insn_p (rinsn))

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c
new file mode 100644 (file)
index 0000000..1da1b8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -O3" } */
+
+#define K 32
+short in[2*K][K];
+short coeff[K][K];
+void
+foo ()
+{
+  for (int j = 0; j < K; j++)
+  {
+    for (int i = 0; i < 2*K; i++)
+      in[i][j] = i+j;
+
+    for (int i = 0; i < K; i++)
+      coeff[i][j] = i + 2;
+  }
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c
index 6b0ff255298a556403654142bb5aa15e9b9a6199..984d5593160f69df71fb297a3e10dad2fd1f240b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c
@@ -5,7 +5,7 @@
 
 void f (int8_t * restrict in, int8_t * restrict out, int n, int cond)
 {
-  size_t vl = 101;
+  size_t vl = 101 + cond;
   for (size_t i = 0; i < n; i++)
     {
       vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
index b5b31fdb5939994800e079ece35c71f10d803388..5b2b2e1e32a843a202c82a72c1b2e655a6bafb9b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
@@ -171,7 +171,7 @@ void f6 (int * restrict in, int * restrict out, int n, int cond)
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
index d2ec69a76f8452bc863f527e03b211cbf712e76b..618e81285a17283fb5e530175dd96ddf851300f3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
@@ -171,7 +171,7 @@ void f6 (int * restrict in, int * restrict out, int n, int cond)
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
index 9fdc8aee6a152d27165dd7a0249f4da9f66920c3..6bdb2e9d1827e014d148e4806e50881cc50d3eab 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
@@ -31,4 +31,4 @@ void f6 (int * restrict in, int * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
index e4caff3f9d158a0474bf4cf0328387b30713d62b..db4f9a1da86282610b40e81668d3fbdad899fa8f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
@@ -199,5 +199,5 @@ void f7 (int * restrict in, int * restrict out, int n, int cond)
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 6 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 6 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c
index 9dc7392556a160ca6ff919f31b78e9d13468cc1a..830dfb83e6d4fc4865b95929d2e3ce56ce846f8c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,\.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,\.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c
index e132c036e7d42052e95b2e018a061dc03f152ddf..898dd20b0ccc404cce0c4ae18cdf25795667c22f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c
index 10eb69a676e823f4f7d9ab187d81d876420fca04..24a3f55d92bd9791f5e681e98481bb84ac9ce3be 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c
index fb13306a13ba1607aec6ab74564f8ab15af9c160..f311cbfc12ae13b3f67fd2c3568bca3e6ea5810c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c
index bfa51c0188e5df2daf511f011b70f74520d27950..2e0fbc5a817058093832eb6d0b2ae10bf3f0090e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c
index 402ec1bbccd2eaa6e0b237540d7872d24f86a759..7a0e12f0ff381dffd137a5a49cc55c0dac204f97 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c
@@ -214,4 +214,4 @@ void f7 (void * restrict in, void * restrict out, int n, int cond)
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vlm\.v\s+v[0-9]+,0\([a-x0-9]+\)} 7 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vlm\.v\s+v[0-9]+,0\([a-x0-9]+\)} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c
index 1389c162f3647aa64955551f1e08a461bb02d6f2..f61260780f2cace28bec8d547894e7ffb18cf5f8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c
index 5e3dd66493153d65a4d0b8f20f71742a9f9dce30..4dcbf7bd1dfaa4520f27763f6cd3b8a8999bf00e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c
index 0de0549c19fc75e7e9737e1283a2d1e13559c09b..0e0b67c5c61fc07381b1ae60718c238299837112 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c
index e76f934b8fe457b283f349786b11d3ddc33af7e4..5a5b7d576070333ba9308a3147054f20438eea24 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c
index c544b9b9d14a00bdaa7e8a1b4d0d5242b58a4bdd..9e1f9c757c05c3c69f2f8399bb29f47fc67aed7f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"   } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"   } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"   } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c
index 7caccee722693dc9e2959c9db11831a9f56433c2..5ac8e179e73149f4646958682a8f731480d83f2b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g"  no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c
index 5a3c986ade111ea60ff471911d82e972cf969bbe..5ac73a979ebc46a369e2be6745e40253dd1edb0b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c
index 5ef9c607038136272a4b049099d04740dd65fa35..f79559c48cd99a549ce5ebe068194977cc27c5b5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c
index 46621b04b9e34891162cf7cf10bfbfcf0e5ee735..a423c5dff28bf6aec6b513eb06ecdb7183a6f252 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c
index 50e484677f0b84e151724f46f25a430b3476112b..00d2f82c2d04db9fa89efda8ff62def687b6d67b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c
index 3d8bdbc1ef00707b10d0bc8b2cc3cf9a475e6f49..69f21e5cf95311a2dce5cefb26349eab3fd9e61b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c
index c4ffa48fccd18477fc6c86f5682a208824c17a67..65709cd5f4262d0b063e90d4394356219cdddeda 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c
index ee4be66b3601ccf80e9622c2860d686ef5a91c58..4bf37250345711114404e7d05e30c76e1dc4455c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c
index d521e427b881671d1b846ccf7fc55fe0ddb7e87c..cacd290168ef269944e7cddbe47c99d750d8800b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c
index f215ac5ffba6bdf7a318d887312d5609f7879186..39e747bd89a01ea93c820f1149e171b27348ce1e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c
@@ -234,4 +234,4 @@ void f7 (void * restrict in, void * restrict out, int n, int cond)
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vlm\.v\s*v[0-9]+,0\([a-x0-9]+\)} 7 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vlm\.v\s*v[0-9]+,0\([a-x0-9]+\)} 7 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto"  } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c
index 3121f43384038367abeabf6765fa16eb1ca06bea..dedadcb53517f46e3a8668212b3eeb8c1c0cc155 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g"   no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g"   no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g"   no-opts "-flto" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c
index 1009517c60916432e489172ecc8f84bc3b0e2845..31be96662a4f6867f7cda51ca1006c0709d68537 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g"  no-opts "-flto"  } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g"  no-opts "-flto"  } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g"  no-opts "-flto"  } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c
index 7c8e5d3d859589254d3edc3e110db851da049b2e..5a48b997a71409abe16b82efc1c6d9ebeb6d3e7c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c
index 35bb54eaef129b7951b3f9aa2cacaf4c9f8d5524..8ea534918caccb7247489570baf09530a5a59c15 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c
index 1d766651ce64fef5a35e20340c6605a62d02bff2..f4fa2696a1dec4dd7aceb767d3c139b67fa30e56 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c
index 8c401140e8250ba36c6f9227c5a20eff90680246..8526ae610d323e276537a0f5cebf4e4ab3a24026 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c
index c6f9c0904cf1a5d8c2001767100db3b2dd0fc2b0..42180a70ab481227622f9ab75d00e13d448b0b74 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int cond)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times {ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c
index 1702885796a91d603fdf8db8ca15bd2aebdaa966..9d40a13b06e6206c31762dabf3d280f6cac571cb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c
@@ -23,4 +23,4 @@ void f (void * restrict in, void * restrict out, int n)
 }
 
 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0"  no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-funroll-loops" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-funroll-loops" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" } } } } */