clk: ingenic: Fix incorrect data for the i2s clock

The register field for configuring the divider for the i2s clock
occupies the bits [8-0], which means 9 bits and not 8.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index 32fcc75f6f77e362279775dd9b20444660347911..bc073dd4470df3de79ccb2c66df4c84ab6110342 100644 (file)
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -134,7 +134,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
                "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
                .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
                .mux = { CGU_REG_CPCCR, 31, 1 },
-               .div = { CGU_REG_I2SCDR, 0, 1, 8, -1, -1, -1 },
+               .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
                .gate = { CGU_REG_CLKGR, 6 },
        },