RISC-V: Add support for Smcdeleg and Ssccfg extensions.

This patch rebases the original patch from Nelson's implement[1].

Added new extension Smcdeleg and Ssccfg with a new CSR, scountinhibit.[2]

Co-Authored-By: Nelson Chu  <nelson@rivosinc.com>
Co-Authored-By: Jiawei Chen <jiawei@iscas.ac.cn>
[1] https://patchwork.sourceware.org/project/binutils/patch/20240620045359.47513-1-nelson@rivosinc.com/
[2] https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/tag/v1.0.0

bfd/ChangeLog:

	* elfxx-riscv.c: New extensions.

gas/ChangeLog:

	* NEWS: Mention new extensions.
	* config/tc-riscv.c (enum riscv_csr_class): New CSR class.
	(riscv_csr_address): Add support for Ssccfg.
	* testsuite/gas/riscv/csr-version-1p10.d: New test for Ssccfg CSR.
	* testsuite/gas/riscv/csr-version-1p10.l: New warning for Ssccfg CSR.
	* testsuite/gas/riscv/csr-version-1p11.d: New test for Ssccfg CSR.
	* testsuite/gas/riscv/csr-version-1p11.l: New warning for Ssccfg CSR.
	* testsuite/gas/riscv/csr-version-1p12.d: New test for Ssccfg CSR.
	* testsuite/gas/riscv/csr-version-1p12.l: New warning for Ssccfg CSR.
	* testsuite/gas/riscv/csr-version-1p13.d: New test for Ssccfg CSR.
	* testsuite/gas/riscv/csr-version-1p13.l: New warning for Ssccfg CSR.
	* testsuite/gas/riscv/csr.s: New Ssccfg CSR.
	* testsuite/gas/riscv/imply.d: New imply check.
	* testsuite/gas/riscv/imply.s: New implies.
	* testsuite/gas/riscv/march-help.l: New helping info.

include/ChangeLog:

        * opcode/riscv-opc.h (CSR_SCOUNTINHIBIT): New CSR address.
        (DECLARE_CSR): Add Ssccfg CSR.

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 007eedb3b239a7322271a28c7c0a09a18e6e9eef..bcb8de49bd3546f2d6014dbe198f5267b359cf5e 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1283,6 +1283,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvks", "+zvksed,+zvksh,+zvkb,+zvkt", check_implicit_always},
 
   {"smaia", "+ssaia", check_implicit_always},
+  {"smcdeleg", "+ssccfg", check_implicit_always},
   {"smcsrind", "+sscsrind", check_implicit_always},
   {"smcntrpmf", "+zicsr", check_implicit_always},
   {"smctr", "+zicsr", check_implicit_always},
@@ -1293,6 +1294,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"smmpm", "+zicsr", check_implicit_always},
 
   {"ssaia", "+zicsr", check_implicit_always},
+  {"ssccfg", "+sscsrind", check_implicit_always},
   {"sscsrind", "+zicsr", check_implicit_always},
   {"sscofpmf", "+zicsr", check_implicit_always},
   {"sscounterenw", "+zicsr", check_implicit_always},
@@ -1481,6 +1483,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
   {"shvstvala",                ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"shvstvecd",                ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"smaia",            ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
+  {"smcdeleg",         ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"smcsrind",         ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"smcntrpmf",                ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"smctr",            ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
@@ -1489,6 +1492,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
   {"smstateen",                ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"smdbltrp",         ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"ssaia",            ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
+  {"ssccfg",           ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"ssccptr",          ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"sscsrind",         ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"sscofpmf",         ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },

diff --git a/gas/NEWS b/gas/NEWS
index 42c3329d83ef7315bc4e0665e0da5eaf747b031e..f28a971736e26d5aae0210abe7f9232c04c87b7a 100644 (file)
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -12,7 +12,7 @@
 
 * Add support for RISC-V standard extensions:
   ssqosid v1.0, ssnpm v1.0, smnpm v1.0, smmpm v1.0, sspm v1.0, supm v1.0,
-  sha v1.0, zce v1.0.
+  sha v1.0, zce v1.0, smcdeleg v1.0, ssccfg v1.0.
 
 * Add support for RISC-V vendor extensions:
   T-Head: xtheadvdot v1.0.

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index a35288e55cb1ca3b91db81049e0ff049786d7d09..737f31ab4017d1fb33952b1e2c215ba1f52d5963 100644 (file)
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -93,6 +93,7 @@ enum riscv_csr_class
   CSR_CLASS_SSAIA_AND_H_32,    /* Ssaia with H, rv32 only */
   CSR_CLASS_SSAIA_OR_SSCSRIND,         /* Ssaia/Smcsrind */
   CSR_CLASS_SSAIA_OR_SSCSRIND_AND_H,   /* Ssaia/Smcsrind with H */
+  CSR_CLASS_SSCCFG,            /* Ssccfg */
   CSR_CLASS_SSCSRIND,          /* Sscsrind */
   CSR_CLASS_SSCSRIND_AND_H,    /* Sscsrind with H */
   CSR_CLASS_SSSTATEEN,         /* S[ms]stateen only */
@@ -1118,6 +1119,9 @@ riscv_csr_address (const char *csr_name,
       is_h_required = (csr_class == CSR_CLASS_SSAIA_OR_SSCSRIND_AND_H);
       extension = "ssaia or sscsrind";
       break;
+    case CSR_CLASS_SSCCFG:
+      extension = "ssccfg";
+      break;
     case CSR_CLASS_SSCSRIND:
     case CSR_CLASS_SSCSRIND_AND_H:
       is_h_required = (csr_class == CSR_CLASS_SSCSRIND_AND_H);

diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
index ba2fa9e5638352258a8efae97a5699660c5f0cc5..f05b3b55585aaee00e463c8336bdb9e687aaf2e7 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p10.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
@@ -739,6 +739,8 @@ Disassembly of section .text:
 [      ]+[0-9a-f]+:[   ]+21459073[     ]+csrw[         ]+vsieh,a1
 [      ]+[0-9a-f]+:[   ]+25402573[     ]+csrr[         ]+a0,vsiph
 [      ]+[0-9a-f]+:[   ]+25459073[     ]+csrw[         ]+vsiph,a1
+[      ]+[0-9a-f]+:[   ]+12002573[     ]+csrr[         ]+a0,scountinhibit
+[      ]+[0-9a-f]+:[   ]+12059073[     ]+csrw[         ]+scountinhibit,a1
 [      ]+[0-9a-f]+:[   ]+01102573[     ]+csrr[         ]+a0,ssp
 [      ]+[0-9a-f]+:[   ]+01159073[     ]+csrw[         ]+ssp,a1
 [      ]+[0-9a-f]+:[   ]+15002573[     ]+csrr[         ]+a0,siselect

diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l
index 0f8e0ece25fae7e70898e59072027cc877d93842..4b6f57389ee8812c933dc8d64f01af26f8783dd9 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p10.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.l
@@ -1301,6 +1301,10 @@
 .*Info: macro .*
 .*Warning: invalid CSR `vsiph', needs `ssaia' extension
 .*Info: macro .*
+.*Warning: invalid CSR `scountinhibit', needs `ssccfg' extension
+.*Info: macro .*
+.*Warning: invalid CSR `scountinhibit', needs `ssccfg' extension
+.*Info: macro .*
 .*Warning: invalid CSR `ssp', needs `zicfiss' extension
 .*Info: macro .*
 .*Warning: invalid CSR `ssp', needs `zicfiss' extension

diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
index ed848981d3f92c199d51c42bd291ee063d36b769..f2f8af9046ea809abdcd761370ddb70d20e21975 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p11.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
@@ -739,6 +739,8 @@ Disassembly of section .text:
 [      ]+[0-9a-f]+:[   ]+21459073[     ]+csrw[         ]+vsieh,a1
 [      ]+[0-9a-f]+:[   ]+25402573[     ]+csrr[         ]+a0,vsiph
 [      ]+[0-9a-f]+:[   ]+25459073[     ]+csrw[         ]+vsiph,a1
+[      ]+[0-9a-f]+:[   ]+12002573[     ]+csrr[         ]+a0,scountinhibit
+[      ]+[0-9a-f]+:[   ]+12059073[     ]+csrw[         ]+scountinhibit,a1
 [      ]+[0-9a-f]+:[   ]+01102573[     ]+csrr[         ]+a0,ssp
 [      ]+[0-9a-f]+:[   ]+01159073[     ]+csrw[         ]+ssp,a1
 [      ]+[0-9a-f]+:[   ]+15002573[     ]+csrr[         ]+a0,siselect

diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l
index 69e6c5318df8568a68b6cd05257016df21db7ded..eb2322b672c63b5c3c83737c40488757b658aca8 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p11.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.l
@@ -1297,6 +1297,10 @@
 .*Info: macro .*
 .*Warning: invalid CSR `vsiph', needs `ssaia' extension
 .*Info: macro .*
+.*Warning: invalid CSR `scountinhibit', needs `ssccfg' extension
+.*Info: macro .*
+.*Warning: invalid CSR `scountinhibit', needs `ssccfg' extension
+.*Info: macro .*
 .*Warning: invalid CSR `ssp', needs `zicfiss' extension
 .*Info: macro .*
 .*Warning: invalid CSR `ssp', needs `zicfiss' extension

diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
index dfbb243e430c5b661c72d3cf2c1716bb6d739e7c..d9d352923bc2868062d35d107596de919e860fb8 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p12.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
@@ -739,6 +739,8 @@ Disassembly of section .text:
 [      ]+[0-9a-f]+:[   ]+21459073[     ]+csrw[         ]+vsieh,a1
 [      ]+[0-9a-f]+:[   ]+25402573[     ]+csrr[         ]+a0,vsiph
 [      ]+[0-9a-f]+:[   ]+25459073[     ]+csrw[         ]+vsiph,a1
+[      ]+[0-9a-f]+:[   ]+12002573[     ]+csrr[         ]+a0,scountinhibit
+[      ]+[0-9a-f]+:[   ]+12059073[     ]+csrw[         ]+scountinhibit,a1
 [      ]+[0-9a-f]+:[   ]+01102573[     ]+csrr[         ]+a0,ssp
 [      ]+[0-9a-f]+:[   ]+01159073[     ]+csrw[         ]+ssp,a1
 [      ]+[0-9a-f]+:[   ]+15002573[     ]+csrr[         ]+a0,siselect

diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l
index 721484130ffc589960ded2a367e545a16b727c58..13c63e196b59f3b21be6d0f5813312b0d59c31d1 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p12.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.l
@@ -1021,6 +1021,10 @@
 .*Info: macro .*
 .*Warning: invalid CSR `vsiph', needs `ssaia' extension
 .*Info: macro .*
+.*Warning: invalid CSR `scountinhibit', needs `ssccfg' extension
+.*Info: macro .*
+.*Warning: invalid CSR `scountinhibit', needs `ssccfg' extension
+.*Info: macro .*
 .*Warning: invalid CSR `ssp', needs `zicfiss' extension
 .*Info: macro .*
 .*Warning: invalid CSR `ssp', needs `zicfiss' extension

diff --git a/gas/testsuite/gas/riscv/csr-version-1p13.d b/gas/testsuite/gas/riscv/csr-version-1p13.d
index 130903043471420f8081cf86c2f4c725f695336f..5d3cef8c4dafe7f42b39d6d152587415689266ce 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p13.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p13.d
@@ -739,6 +739,8 @@ Disassembly of section .text:
 [      ]+[0-9a-f]+:[   ]+21459073[     ]+csrw[         ]+vsieh,a1
 [      ]+[0-9a-f]+:[   ]+25402573[     ]+csrr[         ]+a0,vsiph
 [      ]+[0-9a-f]+:[   ]+25459073[     ]+csrw[         ]+vsiph,a1
+[      ]+[0-9a-f]+:[   ]+12002573[     ]+csrr[         ]+a0,scountinhibit
+[      ]+[0-9a-f]+:[   ]+12059073[     ]+csrw[         ]+scountinhibit,a1
 [      ]+[0-9a-f]+:[   ]+01102573[     ]+csrr[         ]+a0,ssp
 [      ]+[0-9a-f]+:[   ]+01159073[     ]+csrw[         ]+ssp,a1
 [      ]+[0-9a-f]+:[   ]+15002573[     ]+csrr[         ]+a0,siselect

diff --git a/gas/testsuite/gas/riscv/csr-version-1p13.l b/gas/testsuite/gas/riscv/csr-version-1p13.l
index 42c8523a5ee2aab79f5298aaf9009e1d18511235..a705581799673aa3b390ecc8ab5f92e4f1e6506a 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p13.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p13.l
@@ -1017,6 +1017,10 @@
 .*Info: macro .*
 .*Warning: invalid CSR `vsiph', needs `ssaia' extension
 .*Info: macro .*
+.*Warning: invalid CSR `scountinhibit', needs `ssccfg' extension
+.*Info: macro .*
+.*Warning: invalid CSR `scountinhibit', needs `ssccfg' extension
+.*Info: macro .*
 .*Warning: invalid CSR `ssp', needs `zicfiss' extension
 .*Info: macro .*
 .*Warning: invalid CSR `ssp', needs `zicfiss' extension

diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s
index f4c215dd5599670af4d83fbd9179f7d3ce6adfd6..79206444fa327be2b8a3eb14439d9a9267528a20 100644 (file)
--- a/gas/testsuite/gas/riscv/csr.s
+++ b/gas/testsuite/gas/riscv/csr.s
@@ -418,6 +418,9 @@
        csr vsieh
        csr vsiph
 
+       # Ssccfg or Smcdeleg
+       csr scountinhibit
+
        # Zicfiss
        csr ssp
 

diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d
index aa9c1c0458feff974b962119b2432fde29de35cd..988524fdffcac173e4bb3e3d36b20bfaeead63a1 100644 (file)
--- a/gas/testsuite/gas/riscv/imply.d
+++ b/gas/testsuite/gas/riscv/imply.d
@@ -85,12 +85,14 @@ SYMBOL TABLE:
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_smaia1p0_ssaia1p0
+[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_smcdeleg1p0_ssccfg1p0_sscsrind1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_smcsrind1p0_sscsrind1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_smcntrpmf1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_smstateen1p0_ssstateen1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_smepmp1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_smdbltrp1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_ssaia1p0
+[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_ssccfg1p0_sscsrind1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_sscsrind1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_sscofpmf1p0
 [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_sscounterenw1p0

diff --git a/gas/testsuite/gas/riscv/imply.s b/gas/testsuite/gas/riscv/imply.s
index be3c420a9da60fc3606007e01624475c897145b5..de1f0dfc24d71127c6aea1494aa39f944060da34 100644 (file)
--- a/gas/testsuite/gas/riscv/imply.s
+++ b/gas/testsuite/gas/riscv/imply.s
@@ -99,6 +99,7 @@ imply zvksc
 imply zvks
 
 imply smaia
+imply smcdeleg
 imply smcsrind
 imply smcntrpmf
 imply smstateen
@@ -106,6 +107,7 @@ imply smepmp
 imply smdbltrp
 
 imply ssaia
+imply ssccfg
 imply sscsrind
 imply sscofpmf
 imply sscounterenw

diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 25b78eb1177d340eeae47c15c5bc9c1efd05ed13..b4908e5885f337741eea2fdfc1fbbfaee547623b 100644 (file)
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -118,6 +118,7 @@ All available -march extensions for RISC-V:
        shvstvala                               1.0
        shvstvecd                               1.0
        smaia                                   1.0
+       smcdeleg                                1.0
        smcsrind                                1.0
        smcntrpmf                               1.0
        smctr                                   1.0
@@ -126,6 +127,7 @@ All available -march extensions for RISC-V:
        smstateen                               1.0
        smdbltrp                                1.0
        ssaia                                   1.0
+       ssccfg                                  1.0
        ssccptr                                 1.0
        sscsrind                                1.0
        sscofpmf                                1.0

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index c20cb20c5c1c9d35f0b77dd531f2ab56a93e6981..1c649628390f4f46733a8137c3ee7310120e7782 100644 (file)
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -4207,6 +4207,8 @@
 #define CSR_HVIPRIO2H 0x657
 #define CSR_VSIEH     0x214
 #define CSR_VSIPH     0x254
+/* Ssccfg CSR address.  */
+#define CSR_SCOUNTINHIBIT 0x120
 /* Sscsrind extension */
 #define CSR_SIREG2    0x152
 #define CSR_SIREG3    0x153
@@ -5351,6 +5353,8 @@ DECLARE_CSR(hviprio1h, CSR_HVIPRIO1H, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_
 DECLARE_CSR(hviprio2h, CSR_HVIPRIO2H, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(vsieh, CSR_VSIEH, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(vsiph, CSR_VSIPH, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+/* Ssccfg CSR.  */
+DECLARE_CSR(scountinhibit, CSR_SCOUNTINHIBIT, CSR_CLASS_SSCCFG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 /* Sscsrind extension */
 DECLARE_CSR(sireg2, CSR_SIREG2, CSR_CLASS_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(sireg3, CSR_SIREG3, CSR_CLASS_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)