RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets

This is a follow-up to the patch below to avoid generating unrecognized
vsetivl instructions for XTheadVector.

https://gcc.gnu.org/pipermail/gcc-patches/2025-January/674185.html

	PR target/118601

gcc/ChangeLog:

	* config/riscv/riscv-string.cc (expand_block_move): Check with new
	constraint 'vl' instead of 'K'.
	(expand_vec_setmem): Likewise.
	(expand_vec_cmpmem): Likewise.
	* config/riscv/riscv-v.cc (force_vector_length_operand): Likewise.
	(expand_load_store): Likewise.
	(expand_strided_load): Likewise.
	(expand_strided_store): Likewise.
	(expand_lanes_load_store): Likewise.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/xtheadvector/pr114194.c: Move to...
	* gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c: ...here.
	* gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c: New test.
	* gcc.target/riscv/rvv/xtheadvector/pr118601.c: New test.

Reported-by: Edwin Lu <ewlu@rivosinc.com>

diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index 97e20bdb00263738d4b1ef092cf5e08a365ac993..408eb07e87f38776d332e0718718aa78b906a1eb 100644 (file)
--- a/gcc/config/riscv/riscv-string.cc
+++ b/gcc/config/riscv/riscv-string.cc
@@ -1275,7 +1275,7 @@ expand_block_move (rtx dst_in, rtx src_in, rtx length_in, bool movmem_p)
       machine_mode mask_mode = riscv_vector::get_vector_mode
        (BImode, GET_MODE_NUNITS (info.vmode)).require ();
       rtx mask =  CONSTM1_RTX (mask_mode);
-      if (!satisfies_constraint_K (cnt))
+      if (!satisfies_constraint_vl (cnt))
        cnt= force_reg (Pmode, cnt);
       rtx m_ops[] = {vec, mask, src};
       emit_nonvlmax_insn (code_for_pred_mov (info.vmode),
@@ -1626,7 +1626,7 @@ expand_vec_setmem (rtx dst_in, rtx length_in, rtx fill_value_in)
     }
   else
     {
-      if (!satisfies_constraint_K (info.avl))
+      if (!satisfies_constraint_vl (info.avl))
        info.avl = force_reg (Pmode, info.avl);
       emit_nonvlmax_insn (code_for_pred_broadcast (info.vmode),
                          riscv_vector::UNARY_OP, broadcast_ops, info.avl);
@@ -1694,7 +1694,7 @@ expand_vec_cmpmem (rtx result_out, rtx blk_a_in, rtx blk_b_in, rtx length_in)
     }
   else
     {
-      if (!satisfies_constraint_K (length_in))
+      if (!satisfies_constraint_vl (length_in))
              length_in = force_reg (Pmode, length_in);
 
       rtx memmask = CONSTM1_RTX (mask_mode);

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 9847439ca779cbb48a29e485d58e035f40d544d5..62456c7ef79df513d188027b5ffb80925760dce5 100644 (file)
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2103,7 +2103,7 @@ get_unknown_min_value (machine_mode mode)
 static rtx
 force_vector_length_operand (rtx vl)
 {
-  if (CONST_INT_P (vl) && !satisfies_constraint_K (vl))
+  if (CONST_INT_P (vl) && !satisfies_constraint_vl (vl))
     return force_reg (Pmode, vl);
   return vl;
 }
@@ -4130,7 +4130,7 @@ expand_load_store (rtx *ops, bool is_load)
     }
   else
     {
-      if (!satisfies_constraint_K (len))
+      if (!satisfies_constraint_vl (len))
        len = force_reg (Pmode, len);
       if (is_load)
        {
@@ -4165,7 +4165,7 @@ expand_strided_load (machine_mode mode, rtx *ops)
     emit_vlmax_insn (icode, BINARY_OP_TAMA, emit_ops);
   else
     {
-      len = satisfies_constraint_K (len) ? len : force_reg (Pmode, len);
+      len = satisfies_constraint_vl (len) ? len : force_reg (Pmode, len);
       emit_nonvlmax_insn (icode, BINARY_OP_TAMA, emit_ops, len);
     }
 }
@@ -4191,7 +4191,7 @@ expand_strided_store (machine_mode mode, rtx *ops)
     }
   else
     {
-      len = satisfies_constraint_K (len) ? len : force_reg (Pmode, len);
+      len = satisfies_constraint_vl (len) ? len : force_reg (Pmode, len);
       vl_type = get_avl_type_rtx (NONVLMAX);
     }
 
@@ -4642,7 +4642,7 @@ expand_lanes_load_store (rtx *ops, bool is_load)
     }
   else
     {
-      if (!satisfies_constraint_K (len))
+      if (!satisfies_constraint_vl (len))
        len = force_reg (Pmode, len);
       if (is_load)
        {

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c
new file mode 100644 (file)
index 0000000..f95e713
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c
@@ -0,0 +1,51 @@
+/* { dg-do compile { target { { ! riscv_abi_e } && rv32 } } } */
+/* { dg-options "-march=rv32gc_xtheadvector -O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** foo0_1:
+**     sb\tzero,0\([a-x0-9]+\)
+**     ret
+*/
+void foo0_1 (void *p)
+{
+  __builtin_memset (p, 0, 1);
+}
+
+/*
+** foo0_7:
+**     li\t[a-x0-9]+,7
+**     th.vsetvli\tzero,[a-x0-9]+,e8,m1
+**     th\.vmv\.v\.i\tv[0-9],0
+**     th\.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+**     ret
+*/
+void foo0_7 (void *p)
+{
+  __builtin_memset (p, 0, 7);
+}
+
+/*
+** foo1_1:
+**     li\t[a-x0-9]+,1
+**     sb\t[a-x0-9]+,0\([a-x0-9]+\)
+**     ret
+*/
+void foo1_1 (void *p)
+{
+  __builtin_memset (p, 1, 1);
+}
+
+/*
+** foo1_5:
+**     li\t[a-x0-9]+,5
+**     th.vsetvli\tzero,[a-x0-9]+,e8,m1
+**     th\.vmv\.v\.i\tv[0-9],1
+**     th\.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+**     ret
+*/
+
+void foo1_5 (void *p)
+{
+  __builtin_memset (p, 1, 5);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c
similarity index 80%
rename from gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
rename to gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c
index 5c9777b071b516071305d09e6e3366fb201a33da..ee0b49f67c729ddbfc527b152ffc4f621edfa0e4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c
@@ -1,6 +1,5 @@
-/* { dg-do compile { target { ! riscv_abi_e } } } */
-/* { dg-options "-march=rv32gc_xtheadvector -O2" { target { rv32 } } } */
-/* { dg-options "-march=rv64gc_xtheadvector -O2" { target { rv64 } } } */
+/* { dg-do compile { target { { ! riscv_abi_e } && rv64 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector -O2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 /*

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118601.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118601.c
new file mode 100644 (file)
index 0000000..c4ef7a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118601.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target { ! riscv_abi_e } } } */
+/* { dg-options "-march=rv32gc_xtheadvector -O2" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector -O2" { target { rv64 } } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** foo1_16:
+**     li\t[a-x0-9]+,16
+**     th.vsetvli\tzero,[a-x0-9]+,e8,m1
+**     th\.vmv\.v\.i\tv[0-9],1
+**     th\.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+**     ret
+*/
+
+void foo1_16 (void *p)
+{
+   __builtin_memset (p, 1, 16);
+}