drm/msm/a8xx: Fix RSCC offset

In A8xx, the RSCC block is part of GPU's register space. Update the
virtual base address of rscc to point to the correct address.

Fixes: 50e8a557d8d3 ("drm/msm/a8xx: Add support for A8x GMU")
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/727117/
Message-ID: <20260522-glymur-gpu-dt-v5-1-562c406b210c@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index b7166a883b018f459caae742e9a589f32167f8d2..616198a836a4ddea17ecbd1fdd175e9c9c9656ec 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -2401,7 +2401,12 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
                        goto err_mmio;
                }
        } else if (adreno_is_a8xx(adreno_gpu)) {
-               gmu->rscc = gmu->mmio + 0x19000;
+               /*
+                * On a8xx , RSCC lives at GPU base + 0x50000, which falls
+                * inside the GPU's kgsl_3d0_reg_memory range rather than the
+                * GMU's.
+                */
+               gmu->rscc = gpu->mmio + 0x50000;
        } else {
                gmu->rscc = gmu->mmio + 0x23000;
        }