arm64: dts: exynosautov920: add ufs phy for ExynosAutov920 SoC

Add UFS Phy for ExynosAutov920

Like ExynosAutov9, this also uses fixed-rate clock nodes until clock driver
has been supported. The clock nodes are initialized on bootloader stage
thus we don't need to control them so far.

Changes from v4:
- Place entry in correct order instead of appending to the end.

Signed-off-by: Sowon Na <sowon.na@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20250219073731.853120-1-sowon.na@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index a3fd503c1b2123f5ce08192952e20e42ab374dda..fc6ac531d597ec8c93258746b9614d4cd06fd290 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
@@ -567,6 +567,17 @@
                        interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
                };
 
+               ufs_0_phy: phy@16e04000 {
+                       compatible = "samsung,exynosautov920-ufs-phy";
+                       reg = <0x16e04000 0x4000>;
+                       reg-names = "phy-pma";
+                       clocks = <&xtcxo>;
+                       clock-names = "ref_clk";
+                       samsung,pmu-syscon = <&pmu_system_controller>;
+                       #phy-cells = <0>;
+                       status = "disabled";
+               };
+
                pinctrl_aud: pinctrl@1a460000 {
                        compatible = "samsung,exynosautov920-pinctrl";
                        reg = <0x1a460000 0x10000>;