]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/i915/cdclk: abstract intel_cdclk_logical()
authorJani Nikula <jani.nikula@intel.com>
Wed, 25 Jun 2025 10:32:27 +0000 (13:32 +0300)
committerJani Nikula <jani.nikula@intel.com>
Thu, 26 Jun 2025 08:55:53 +0000 (11:55 +0300)
Add intel_cdclk_logical() helper to avoid looking at struct
intel_cdclk_state internals outside of intel_cdclk.c.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://lore.kernel.org/r/e965667550e82307341d6abbeedc67b93cae9fc6.1750847509.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/hsw_ips.c
drivers/gpu/drm/i915/display/intel_cdclk.c
drivers/gpu/drm/i915/display/intel_cdclk.h
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/display/intel_fbc.c
drivers/gpu/drm/i915/display/skl_watermark.c

index 989a9171b07f1fcb922df0cf3876b56e8670a984..927fe56aec777416327db31987b631ffb3d4320f 100644 (file)
@@ -265,7 +265,7 @@ int hsw_ips_compute_config(struct intel_atomic_state *state,
                        return PTR_ERR(cdclk_state);
 
                /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
-               if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
+               if (crtc_state->pixel_rate > intel_cdclk_logical(cdclk_state) * 95 / 100)
                        return 0;
        }
 
index 95fab2ee3d9420841893ad77b3563b7c0c8cfd7b..51485c777b6236312469d00e4b846f93c839296e 100644 (file)
@@ -3834,3 +3834,8 @@ void intel_init_cdclk_hooks(struct intel_display *display)
                     "Unknown platform. Assuming i830\n"))
                display->funcs.cdclk = &i830_cdclk_funcs;
 }
+
+int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state)
+{
+       return cdclk_state->logical.cdclk;
+}
index a1cefd455d92a8b4d3f57ceb2e2f986761319527..20a66f6130728bcbeab3144edc8f6a9949a2564a 100644 (file)
@@ -97,4 +97,6 @@ void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc);
 int intel_cdclk_init(struct intel_display *display);
 void intel_cdclk_debugfs_register(struct intel_display *display);
 
+int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state);
+
 #endif /* __INTEL_CDCLK_H__ */
index de8bf292897cba457bdf6c7ae694219de456c745..cd6fa16690748769d46dae087f6ff12a049a94fc 100644 (file)
@@ -4168,7 +4168,7 @@ static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
                return 0;
 
        linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
-                                       cdclk_state->logical.cdclk);
+                                       intel_cdclk_logical(cdclk_state));
 
        return min(linetime_wm, 0x1ff);
 }
index ec1ef8694c356cabdfce5827a3e48c156273636d..5d28a6062db13f31848fecebd9e33b6393587373 100644 (file)
@@ -1576,7 +1576,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
                if (IS_ERR(cdclk_state))
                        return PTR_ERR(cdclk_state);
 
-               if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) {
+               if (crtc_state->pixel_rate >= intel_cdclk_logical(cdclk_state) * 95 / 100) {
                        plane_state->no_fbc_reason = "pixel rate too high";
                        return 0;
                }
index f98c4a0fc7a9785776343f2074e81f340e0fc679..f234a3aa3d15b3a75641abce61c4a606d8c97a87 100644 (file)
@@ -2178,7 +2178,7 @@ cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
        }
 
        return min(1, DIV_ROUND_UP(crtc_state->pixel_rate,
-                                  2 * cdclk_state->logical.cdclk));
+                                  2 * intel_cdclk_logical(cdclk_state)));
 }
 
 static int