drop another i915 patch that broke the build

diff --git a/queue-5.3/drm-i915-flush-extra-hard-after-writing-relocations-through-the-gtt.patch b/queue-5.3/drm-i915-flush-extra-hard-after-writing-relocations-through-the-gtt.patch
deleted file mode 100644 (file)
index ce7f8ff..0000000
--- a/queue-5.3/drm-i915-flush-extra-hard-after-writing-relocations-through-the-gtt.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From 576f05865581f82ac988ffec70e4e2ebd31165db Mon Sep 17 00:00:00 2001
-From: Chris Wilson <chris@chris-wilson.co.uk>
-Date: Tue, 30 Jul 2019 12:21:51 +0100
-Subject: drm/i915: Flush extra hard after writing relocations through the GTT
-
-From: Chris Wilson <chris@chris-wilson.co.uk>
-
-commit 576f05865581f82ac988ffec70e4e2ebd31165db upstream.
-
-Recently discovered in commit bdae33b8b82b ("drm/i915: Use maximum write
-flush for pwrite_gtt") was that we needed to our full write barrier
-before changing the GGTT PTE to ensure that our indirect writes through
-the GTT landed before the PTE changed (and the writes end up in a
-different page). That also applies to our GGTT relocation path.
-
-Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
-Cc: stable@vger.kernel.org
-Reviewed-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
-Link: https://patchwork.freedesktop.org/patch/msgid/20190730112151.5633-4-chris@chris-wilson.co.uk
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-
----
- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c |    9 +++++----
- 1 file changed, 5 insertions(+), 4 deletions(-)
-
---- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
-+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
-@@ -1018,11 +1018,12 @@ static void reloc_cache_reset(struct rel
-               kunmap_atomic(vaddr);
-               i915_gem_object_finish_access((struct drm_i915_gem_object *)cache->node.mm);
-       } else {
--              wmb();
-+              struct i915_ggtt *ggtt = cache_to_ggtt(cache);
-+
-+              intel_gt_flush_ggtt_writes(ggtt->vm.gt);
-               io_mapping_unmap_atomic((void __iomem *)vaddr);
--              if (cache->node.allocated) {
--                      struct i915_ggtt *ggtt = cache_to_ggtt(cache);
- 
-+              if (cache->node.allocated) {
-                       ggtt->vm.clear_range(&ggtt->vm,
-                                            cache->node.start,
-                                            cache->node.size);
-@@ -1077,6 +1078,7 @@ static void *reloc_iomap(struct drm_i915
-       void *vaddr;
- 
-       if (cache->vaddr) {
-+              intel_gt_flush_ggtt_writes(ggtt->vm.gt);
-               io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
-       } else {
-               struct i915_vma *vma;
-@@ -1118,7 +1120,6 @@ static void *reloc_iomap(struct drm_i915
- 
-       offset = cache->node.start;
-       if (cache->node.allocated) {
--              wmb();
-               ggtt->vm.insert_page(&ggtt->vm,
-                                    i915_gem_object_get_dma_address(obj, page),
-                                    offset, I915_CACHE_NONE, 0);

diff --git a/queue-5.3/series b/queue-5.3/series
index 4e0feeb33297b08abeaf803ad510c503da8b5c5a..905e345c2d20ae15e43fea29e02fd23e1c831fe6 100644 (file)
--- a/queue-5.3/series
+++ b/queue-5.3/series
@@ -69,7 +69,6 @@ drm-nouveau-kms-nv50-don-t-create-mstms-for-edp-connectors.patch
 drm-amd-powerplay-change-metrics-update-period-from-1ms-to-100ms.patch
 drm-i915-gvt-update-vgpu-workload-head-pointer-correctly.patch
 drm-i915-userptr-acquire-the-page-lock-around-set_page_dirty.patch
-drm-i915-flush-extra-hard-after-writing-relocations-through-the-gtt.patch
 drm-i915-to-make-vgpu-ppgtt-notificaiton-as-atomic-operation.patch
 mac80211-keep-bhs-disabled-while-calling-drv_tx_wake_queue.patch
 mmc-tegra-implement-set_dma_mask.patch