drm/i915/display: rename IS_DISPLAY_IP_STEP() to IS_DISPLAY_VER_STEP()

Unify macro naming on VER.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/6861e02f3adf15d56e89890000eb195070c33c9b.1724180287.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 73d6c865693bc6ef3995fa306a32a4990ea0a461..ccf1710cb9df4d585096afdaac3af8249add32b4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -175,13 +175,13 @@ enum intel_display_subplatform {
  * hardware fix is present and the software workaround is no longer necessary.
  * E.g.,
  *
- *    IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2)
- *    IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER)
+ *    IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2)
+ *    IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER)
  *
  * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper
  * stepping bound for the specified IP version.
  */
-#define IS_DISPLAY_IP_STEP(__i915, ipver, from, until) \
+#define IS_DISPLAY_VER_STEP(__i915, ipver, from, until) \
        (IS_DISPLAY_VER_FULL((__i915), (ipver), (ipver)) && \
         IS_DISPLAY_STEP((__i915), (from), (until)))
 

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 4c91a2b69a09b5726f1a7184da643bd09719fe79..65d8d48d6a9a1da7645cf1fd3f569ea90854d22c 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1340,7 +1340,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
 
        /* Wa_14016291713 */
        if ((IS_DISPLAY_VER(display, 12, 13) ||
-            IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
+            IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
            crtc_state->has_psr && !crtc_state->has_panel_replay) {
                plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
                return 0;

diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 05402ae6b56944321c7a3227ed63a43b260c0015..94418f218448c249fcb00c6e627c708be36dc02b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -42,11 +42,11 @@ intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder,
                return;
 
        if (DISPLAY_VER(dev_priv) >= 14) {
-               if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_D0, STEP_FOREVER))
+               if (IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_D0, STEP_FOREVER))
                        intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(hdcp->cpu_transcoder),
                                     0, HDCP_LINE_REKEY_DISABLE);
-               else if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 1), STEP_B0, STEP_FOREVER) ||
-                        IS_DISPLAY_IP_STEP(dev_priv, IP_VER(20, 0), STEP_B0, STEP_FOREVER))
+               else if (IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 1), STEP_B0, STEP_FOREVER) ||
+                        IS_DISPLAY_VER_STEP(dev_priv, IP_VER(20, 0), STEP_B0, STEP_FOREVER))
                        intel_de_rmw(dev_priv,
                                     TRANS_DDI_FUNC_CTL(dev_priv, hdcp->cpu_transcoder),
                                     0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE);

diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index 9ca981b7a12c125482cd565c4a00832f2a1b06d0..ceaf9e3147dad41cf62bf643800c3b9c8013b320 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
                                     &pmdemand_state->base,
                                     &intel_pmdemand_funcs);
 
-       if (IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0))
+       if (IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0))
                /* Wa_14016740474 */
                intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
 

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 572dcdf77453cbecf409de9229614481a7e867cc..257526362b39a884a80340cc737378781f91caf3 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1868,14 +1868,14 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
                 * cause issues if non-supported panels are used.
                 */
                if (!intel_dp->psr.panel_replay_enabled &&
-                   (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
+                   (IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
                     IS_ALDERLAKE_P(dev_priv)))
                        intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
                                     0, ADLP_1_BASED_X_GRANULARITY);
 
                /* Wa_16012604467:adlp,mtl[a0,b0] */
                if (!intel_dp->psr.panel_replay_enabled &&
-                   IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
+                   IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
                        intel_de_rmw(dev_priv,
                                     MTL_CLKGATE_DIS_TRANS(dev_priv, cpu_transcoder),
                                     0,
@@ -2057,7 +2057,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
        if (intel_dp->psr.sel_update_enabled) {
                /* Wa_16012604467:adlp,mtl[a0,b0] */
                if (!intel_dp->psr.panel_replay_enabled &&
-                   IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
+                   IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
                        intel_de_rmw(dev_priv,
                                     MTL_CLKGATE_DIS_TRANS(dev_priv, cpu_transcoder),
                                     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@@ -2542,7 +2542,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 
        /* Wa_14014971492 */
        if (!crtc_state->has_panel_replay &&
-           ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
+           ((IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
              IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv))) &&
            crtc_state->splitter.enable)
                crtc_state->psr2_su_area.y1 = 0;