RISC-V: Add Zbb orn and its pseudo instruction opcode to rv64gc in riscv.pm

Signed-off-by: Julian Zhu <julian.oerv@isrc.iscas.ac.cn>
Reviewed-by: Paul Yang <paulyang.inf@gmail.com>
Reviewed-by: Paul Dale <ppzgs1@gmail.com>
(Merged from https://github.com/openssl/openssl/pull/27990)

diff --git a/crypto/perlasm/riscv.pm b/crypto/perlasm/riscv.pm
index 69a47c5bcfef9953da055a3ac2b44df5955b5cb6..bac41fb453bd37e21b328f43f7a918b562d18f16 100644 (file)
--- a/crypto/perlasm/riscv.pm
+++ b/crypto/perlasm/riscv.pm
@@ -289,6 +289,15 @@ ___
     return $code;
 }
 
+sub orn_rv64i {
+    my ($rd, $rs1, $rs2) = @_;
+    my $code=<<___;
+    not $rd, $rs2
+    or $rd, $rd, $rs1
+___
+    return $code;
+}
+
 # Scalar crypto instructions
 
 sub aes64ds {
@@ -388,6 +397,16 @@ sub clmulh {
     return ".word ".($template | ($rs2 << 20) | ($rs1 << 15) | ($rd << 7));
 }
 
+sub orn {
+    # Encoding for orn rd, rs1, rs2
+    #               0100000 _ rs2 _ rs1 _110_ rd  _0110011
+    my $template = 0b0100000_00000_00000_110_00000_0110011;
+    my $rd = read_reg shift;
+    my $rs1 = read_reg shift;
+    my $rs2 = read_reg shift;
+    return ".word ".($template | ($rs2 << 20) | ($rs1 << 15) | ($rd << 7));
+}
+
 sub rev8 {
     # Encoding for rev8 rd, rs instruction on RV64
     #               XXXXXXXXXXXXX_ rs  _XXX_ rd  _XXXXXXX