ASoC: fsl_xcvr: Use regmap for PHY and PLL registers

Define regmap for PHY and PLL registers, the PHY and PLL
registers are accessed by AI interface in controller.

So that driver can use regcache to recover registers
after suspend and resume.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://patch.msgid.link/20241127030035.649219-2-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c
index 1e0bfd59d511882a33d7ac11992af8fbe9d0b58d..bbfaa596abc91b58996565a1d87a089a93597ef5 100644 (file)
--- a/sound/soc/fsl/fsl_xcvr.c
+++ b/sound/soc/fsl/fsl_xcvr.c
@@ -37,6 +37,8 @@ struct fsl_xcvr {
        const struct fsl_xcvr_soc_data *soc_data;
        struct platform_device *pdev;
        struct regmap *regmap;
+       struct regmap *regmap_phy;
+       struct regmap *regmap_pll;
        struct clk *ipg_clk;
        struct clk *pll_ipg_clk;
        struct clk *phy_clk;
@@ -257,7 +259,7 @@ static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy)
        idx  = BIT(phy ? 26 : 24);
        tidx = BIT(phy ? 27 : 25);
 
-       regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF);
+       regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF | FSL_XCVR_PHY_AI_CTRL_AI_RWB);
        regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg);
        regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data);
        regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx);
@@ -271,6 +273,59 @@ static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy)
        return ret;
 }
 
+static int fsl_xcvr_ai_read(struct fsl_xcvr *xcvr, u8 reg, u32 *data, bool phy)
+{
+       struct device *dev = &xcvr->pdev->dev;
+       u32 val, idx, tidx;
+       int ret;
+
+       idx  = BIT(phy ? 26 : 24);
+       tidx = BIT(phy ? 27 : 25);
+
+       regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF | FSL_XCVR_PHY_AI_CTRL_AI_RWB);
+       regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg | FSL_XCVR_PHY_AI_CTRL_AI_RWB);
+       regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx);
+
+       ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val,
+                                      (val & idx) == ((val & tidx) >> 1),
+                                      10, 10000);
+       if (ret)
+               dev_err(dev, "AI timeout: failed to read %s reg 0x%02x\n",
+                       phy ? "PHY" : "PLL", reg);
+
+       regmap_read(xcvr->regmap, FSL_XCVR_PHY_AI_RDATA, data);
+
+       return ret;
+}
+
+static int fsl_xcvr_phy_reg_read(void *context, unsigned int reg, unsigned int *val)
+{
+       struct fsl_xcvr *xcvr = context;
+
+       return fsl_xcvr_ai_read(xcvr, reg, val, 1);
+}
+
+static int fsl_xcvr_phy_reg_write(void *context, unsigned int reg, unsigned int val)
+{
+       struct fsl_xcvr *xcvr = context;
+
+       return fsl_xcvr_ai_write(xcvr, reg, val, 1);
+}
+
+static int fsl_xcvr_pll_reg_read(void *context, unsigned int reg, unsigned int *val)
+{
+       struct fsl_xcvr *xcvr = context;
+
+       return fsl_xcvr_ai_read(xcvr, reg, val, 0);
+}
+
+static int fsl_xcvr_pll_reg_write(void *context, unsigned int reg, unsigned int val)
+{
+       struct fsl_xcvr *xcvr = context;
+
+       return fsl_xcvr_ai_write(xcvr, reg, val, 0);
+}
+
 static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx)
 {
        struct device *dev = &xcvr->pdev->dev;
@@ -303,55 +358,55 @@ static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx)
        switch (xcvr->soc_data->pll_ver) {
        case PLL_MX8MP:
                /* PLL: BANDGAP_SET: EN_VBG (enable bandgap) */
-               fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_BANDGAP_SET,
-                                 FSL_XCVR_PLL_BANDGAP_EN_VBG, 0);
+               regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_BANDGAP,
+                               FSL_XCVR_PLL_BANDGAP_EN_VBG);
 
                /* PLL: CTRL0: DIV_INTEGER */
-               fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi, 0);
+               regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi);
                /* PLL: NUMERATOR: MFN */
-               fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn, 0);
+               regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn);
                /* PLL: DENOMINATOR: MFD */
-               fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd, 0);
+               regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd);
                /* PLL: CTRL0_SET: HOLD_RING_OFF, POWER_UP */
-               fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
-                                 FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP, 0);
+               regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0,
+                               FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP);
                udelay(25);
                /* PLL: CTRL0: Clear Hold Ring Off */
-               fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_CLR,
-                                 FSL_XCVR_PLL_CTRL0_HROFF, 0);
+               regmap_clear_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0,
+                                 FSL_XCVR_PLL_CTRL0_HROFF);
                udelay(100);
                if (tx) { /* TX is enabled for SPDIF only */
                        /* PLL: POSTDIV: PDIV0 */
-                       fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
-                                         FSL_XCVR_PLL_PDIVx(log2, 0), 0);
+                       regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV,
+                                    FSL_XCVR_PLL_PDIVx(log2, 0));
                        /* PLL: CTRL_SET: CLKMUX0_EN */
-                       fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
-                                         FSL_XCVR_PLL_CTRL0_CM0_EN, 0);
+                       regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0,
+                                       FSL_XCVR_PLL_CTRL0_CM0_EN);
                } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */
                        /* PLL: POSTDIV: PDIV1 */
-                       fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
-                                         FSL_XCVR_PLL_PDIVx(log2, 1), 0);
+                       regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV,
+                                    FSL_XCVR_PLL_PDIVx(log2, 1));
                        /* PLL: CTRL_SET: CLKMUX1_EN */
-                       fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
-                                         FSL_XCVR_PLL_CTRL0_CM1_EN, 0);
+                       regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0,
+                                       FSL_XCVR_PLL_CTRL0_CM1_EN);
                } else { /* SPDIF / ARC RX */
                        /* PLL: POSTDIV: PDIV2 */
-                       fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
-                                         FSL_XCVR_PLL_PDIVx(log2, 2), 0);
+                       regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV,
+                                    FSL_XCVR_PLL_PDIVx(log2, 2));
                        /* PLL: CTRL_SET: CLKMUX2_EN */
-                       fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
-                                         FSL_XCVR_PLL_CTRL0_CM2_EN, 0);
+                       regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0,
+                                       FSL_XCVR_PLL_CTRL0_CM2_EN);
                }
                break;
        case PLL_MX95:
                val = fsl_xcvr_pll_cfg[i].mfi << FSL_XCVR_GP_PLL_DIV_MFI_SHIFT | div;
-               fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_DIV, val, 0);
+               regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_DIV, val);
                val = fsl_xcvr_pll_cfg[i].mfn << FSL_XCVR_GP_PLL_NUMERATOR_MFN_SHIFT;
-               fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_NUMERATOR, val, 0);
-               fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_DENOMINATOR,
-                                 fsl_xcvr_pll_cfg[i].mfd, 0);
+               regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_NUMERATOR, val);
+               regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_DENOMINATOR,
+                            fsl_xcvr_pll_cfg[i].mfd);
                val = FSL_XCVR_GP_PLL_CTRL_POWERUP | FSL_XCVR_GP_PLL_CTRL_CLKMUX_EN;
-               fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_CTRL, val, 0);
+               regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_CTRL, val);
                break;
        default:
                dev_err(dev, "Error for PLL version %d\n", xcvr->soc_data->pll_ver);
@@ -360,22 +415,22 @@ static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx)
 
        if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
                /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */
-               fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
-                                 FSL_XCVR_PHY_CTRL_TSDIFF_OE |
-                                 FSL_XCVR_PHY_CTRL_PHY_EN, 1);
+               regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL,
+                               FSL_XCVR_PHY_CTRL_TSDIFF_OE |
+                               FSL_XCVR_PHY_CTRL_PHY_EN);
                /* PHY: CTRL2_SET: EARC_TX_MODE */
-               fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET,
-                                 FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1);
+               regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL2,
+                               FSL_XCVR_PHY_CTRL2_EARC_TXMS);
        } else if (!tx) { /* SPDIF / ARC RX mode */
                if (xcvr->mode == FSL_XCVR_MODE_SPDIF)
                        /* PHY: CTRL_SET: SPDIF_EN */
-                       fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
-                                         FSL_XCVR_PHY_CTRL_SPDIF_EN, 1);
+                       regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL,
+                                       FSL_XCVR_PHY_CTRL_SPDIF_EN);
                else    /* PHY: CTRL_SET: ARC RX setup */
-                       fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
-                                         FSL_XCVR_PHY_CTRL_PHY_EN |
-                                         FSL_XCVR_PHY_CTRL_RX_CM_EN |
-                                         fsl_xcvr_phy_arc_cfg[xcvr->arc_mode], 1);
+                       regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL,
+                                       FSL_XCVR_PHY_CTRL_PHY_EN |
+                                       FSL_XCVR_PHY_CTRL_RX_CM_EN |
+                                       fsl_xcvr_phy_arc_cfg[xcvr->arc_mode]);
        }
 
        dev_dbg(dev, "PLL Fexp: %u, Fout: %u, mfi: %u, mfn: %u, mfd: %d, div: %u, pdiv0: %u\n",
@@ -416,17 +471,17 @@ static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq)
 
        if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
                /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */
-               fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
-                                 FSL_XCVR_PHY_CTRL_TSDIFF_OE |
-                                 FSL_XCVR_PHY_CTRL_PHY_EN, 1);
+               regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL,
+                               FSL_XCVR_PHY_CTRL_TSDIFF_OE |
+                               FSL_XCVR_PHY_CTRL_PHY_EN);
                /* PHY: CTRL2_SET: EARC_TX_MODE */
-               fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET,
-                                 FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1);
+               regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL2,
+                               FSL_XCVR_PHY_CTRL2_EARC_TXMS);
        } else { /* SPDIF mode */
                /* PHY: CTRL_SET: TX_CLK_AUD_SS | SPDIF_EN */
-               fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
-                                 FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS |
-                                 FSL_XCVR_PHY_CTRL_SPDIF_EN, 1);
+               regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL,
+                               FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS |
+                               FSL_XCVR_PHY_CTRL_SPDIF_EN);
        }
 
        dev_dbg(dev, "PLL Fexp: %u\n", freq);
@@ -1206,6 +1261,49 @@ static const struct regmap_config fsl_xcvr_regmap_cfg = {
        .cache_type = REGCACHE_FLAT,
 };
 
+static const struct reg_default fsl_xcvr_phy_reg_defaults[] = {
+       { FSL_XCVR_PHY_CTRL,            0x58200804 },
+       { FSL_XCVR_PHY_STATUS,          0x00000000 },
+       { FSL_XCVR_PHY_ANALOG_TRIM,     0x00260F13 },
+       { FSL_XCVR_PHY_SLEW_RATE_TRIM,  0x00000411 },
+       { FSL_XCVR_PHY_DATA_TEST_DELAY, 0x00990000 },
+       { FSL_XCVR_PHY_TEST_CTRL,       0x00000000 },
+       { FSL_XCVR_PHY_DIFF_CDR_CTRL,   0x016D0009 },
+       { FSL_XCVR_PHY_CTRL2,           0x80000000 },
+};
+
+static const struct regmap_config fsl_xcvr_regmap_phy_cfg = {
+       .reg_bits = 8,
+       .reg_stride = 4,
+       .val_bits = 32,
+       .max_register = FSL_XCVR_PHY_CTRL2_TOG,
+       .reg_defaults = fsl_xcvr_phy_reg_defaults,
+       .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_phy_reg_defaults),
+       .cache_type = REGCACHE_FLAT,
+       .reg_read = fsl_xcvr_phy_reg_read,
+       .reg_write = fsl_xcvr_phy_reg_write,
+};
+
+static const struct regmap_config fsl_xcvr_regmap_pllv0_cfg = {
+       .reg_bits = 8,
+       .reg_stride = 4,
+       .val_bits = 32,
+       .max_register = FSL_XCVR_PLL_STAT0_TOG,
+       .cache_type = REGCACHE_FLAT,
+       .reg_read = fsl_xcvr_pll_reg_read,
+       .reg_write = fsl_xcvr_pll_reg_write,
+};
+
+static const struct regmap_config fsl_xcvr_regmap_pllv1_cfg = {
+       .reg_bits = 8,
+       .reg_stride = 4,
+       .val_bits = 32,
+       .max_register = FSL_XCVR_GP_PLL_STATUS_TOG,
+       .cache_type = REGCACHE_FLAT,
+       .reg_read = fsl_xcvr_pll_reg_read,
+       .reg_write = fsl_xcvr_pll_reg_write,
+};
+
 static void reset_rx_work(struct work_struct *work)
 {
        struct fsl_xcvr *xcvr = container_of(work, struct fsl_xcvr, work_rst);
@@ -1421,6 +1519,40 @@ static int fsl_xcvr_probe(struct platform_device *pdev)
                return PTR_ERR(xcvr->regmap);
        }
 
+       if (xcvr->soc_data->use_phy) {
+               xcvr->regmap_phy = devm_regmap_init(dev, NULL, xcvr,
+                                                   &fsl_xcvr_regmap_phy_cfg);
+               if (IS_ERR(xcvr->regmap_phy)) {
+                       dev_err(dev, "failed to init XCVR PHY regmap: %ld\n",
+                               PTR_ERR(xcvr->regmap_phy));
+                       return PTR_ERR(xcvr->regmap_phy);
+               }
+
+               switch (xcvr->soc_data->pll_ver) {
+               case PLL_MX8MP:
+                       xcvr->regmap_pll = devm_regmap_init(dev, NULL, xcvr,
+                                                           &fsl_xcvr_regmap_pllv0_cfg);
+                       if (IS_ERR(xcvr->regmap_pll)) {
+                               dev_err(dev, "failed to init XCVR PLL regmap: %ld\n",
+                                       PTR_ERR(xcvr->regmap_pll));
+                               return PTR_ERR(xcvr->regmap_pll);
+                       }
+                       break;
+               case PLL_MX95:
+                       xcvr->regmap_pll = devm_regmap_init(dev, NULL, xcvr,
+                                                           &fsl_xcvr_regmap_pllv1_cfg);
+                       if (IS_ERR(xcvr->regmap_pll)) {
+                               dev_err(dev, "failed to init XCVR PLL regmap: %ld\n",
+                                       PTR_ERR(xcvr->regmap_pll));
+                               return PTR_ERR(xcvr->regmap_pll);
+                       }
+                       break;
+               default:
+                       dev_err(dev, "Error for PLL version %d\n", xcvr->soc_data->pll_ver);
+                       return -EINVAL;
+               }
+       }
+
        xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL);
        if (IS_ERR(xcvr->reset)) {
                dev_err(dev, "failed to get XCVR reset control\n");

diff --git a/sound/soc/fsl/fsl_xcvr.h b/sound/soc/fsl/fsl_xcvr.h
index c72cb05184df805a42164f19ae8e43f68230d51a..dade3945cc0c5d6bb69df5f7356f5891aa31098d 100644 (file)
--- a/sound/soc/fsl/fsl_xcvr.h
+++ b/sound/soc/fsl/fsl_xcvr.h
@@ -234,6 +234,7 @@
 #define FSL_XCVR_TX_DPTH_CTRL_TM_NO_PRE_BME    GENMASK(31, 30)
 
 #define FSL_XCVR_PHY_AI_CTRL_AI_RESETN         BIT(15)
+#define FSL_XCVR_PHY_AI_CTRL_AI_RWB            BIT(31)
 
 #define FSL_XCVR_PLL_CTRL0                     0x00
 #define FSL_XCVR_PLL_CTRL0_SET                 0x04
@@ -241,13 +242,25 @@
 #define FSL_XCVR_PLL_NUM                       0x20
 #define FSL_XCVR_PLL_DEN                       0x30
 #define FSL_XCVR_PLL_PDIV                      0x40
+#define FSL_XCVR_PLL_BANDGAP                   0x50
 #define FSL_XCVR_PLL_BANDGAP_SET               0x54
+#define FSL_XCVR_PLL_STAT0                     0x60
+#define FSL_XCVR_PLL_STAT0_TOG                 0x6c
+
 #define FSL_XCVR_PHY_CTRL                      0x00
 #define FSL_XCVR_PHY_CTRL_SET                  0x04
 #define FSL_XCVR_PHY_CTRL_CLR                  0x08
+#define FSL_XCVR_PHY_CTRL_TOG                  0x0c
+#define FSL_XCVR_PHY_STATUS                    0x10
+#define FSL_XCVR_PHY_ANALOG_TRIM               0x20
+#define FSL_XCVR_PHY_SLEW_RATE_TRIM            0x30
+#define FSL_XCVR_PHY_DATA_TEST_DELAY           0x40
+#define FSL_XCVR_PHY_TEST_CTRL                 0x50
+#define FSL_XCVR_PHY_DIFF_CDR_CTRL             0x60
 #define FSL_XCVR_PHY_CTRL2                     0x70
 #define FSL_XCVR_PHY_CTRL2_SET                 0x74
 #define FSL_XCVR_PHY_CTRL2_CLR                 0x78
+#define FSL_XCVR_PHY_CTRL2_TOG                 0x7c
 
 #define FSL_XCVR_PLL_BANDGAP_EN_VBG            BIT(0)
 #define FSL_XCVR_PLL_CTRL0_HROFF               BIT(13)