drm/amd/display: Implement Replay Low Hz Visual Confirm

[why]
Add new Visual confirm color for Replay Low Hz.

Reviewed-by: Robin Chen <robin.chen@amd.com>
Signed-off-by: Dennis.Chan <Dennis.Chan@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 778627ddc746d911428e176dcf70caba228aa525..ff5b162f3916988681f535d6a0df640ed36e2668 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -1066,10 +1066,13 @@ enum replay_FW_Message_type {
 
 union replay_error_status {
        struct {
-               unsigned char STATE_TRANSITION_ERROR    :1;
-               unsigned char LINK_CRC_ERROR            :1;
-               unsigned char DESYNC_ERROR              :1;
-               unsigned char RESERVED                  :5;
+               unsigned int STATE_TRANSITION_ERROR     :1;
+               unsigned int LINK_CRC_ERROR             :1;
+               unsigned int DESYNC_ERROR               :1;
+               unsigned int RESERVED_3                 :1;
+               unsigned int LOW_RR_INCORRECT_VTOTAL    :1;
+               unsigned int NO_DOUBLED_RR              :1;
+               unsigned int RESERVED_6_7               :2;
        } bits;
        unsigned char raw;
 };

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
index 48abeaa886780f28e0d4fdefebcb2cf18423c694..017fbc476d51f243c562469ddfa829bf5e445e13 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
@@ -226,6 +226,8 @@ static void handle_hpd_irq_replay_sink(struct dc_link *link)
                replay_configuration.bits.STATE_TRANSITION_ERROR_STATUS) {
                bool allow_active;
 
+               link->replay_settings.config.replay_error_status.raw |= replay_error_status.raw;
+
                if (link->replay_settings.config.force_disable_desync_error_check)
                        return;
 

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 59990929e44e34d3936b0c598f65382e64591179..904309943ec04fc3e53a00782fb8576def9ec709 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -431,7 +431,67 @@ union replay_debug_flags {
                 */
                uint32_t enable_ips_residency_profiling : 1;
 
-               uint32_t reserved : 20;
+               /**
+                * 0x1000 (bit 12)
+                * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check
+                */
+               uint32_t enable_coasting_vtotal_check : 1;
+
+               uint32_t reserved : 19;
+       } bitfields;
+
+       uint32_t u32All;
+};
+
+/**
+ * Flags record error state.
+ */
+union replay_error_state_flags {
+       struct {
+               /**
+                * 0x1 (bit 0) - Desync Error flag.
+                */
+               uint32_t desync_error : 1;
+
+               /**
+                * 0x2 (bit 1) - State Transition Error flag.
+                */
+               uint32_t state_transition_error : 1;
+
+               /**
+                * 0x4 (bit 2) - Crc Error flag
+                */
+               uint32_t crc_error : 1;
+
+               /**
+                * 0x8 (bit 3) - Reserved
+                */
+               uint32_t reserved_3 : 1;
+
+               /**
+                * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write.
+                * Added new debug flag to control DPCD.
+                */
+               uint32_t incorrect_vtotal_in_static_screen : 1;
+
+               /**
+                * 0x20 (bit 5) - No doubled Refresh Rate.
+                */
+               uint32_t no_double_rr : 1;
+
+               /**
+                * Reserved bit 6-7
+                */
+               uint32_t reserved_6_7 : 2;
+               /**
+                * 0x100 (bit 8) - DQE Only.
+                */
+               uint32_t pass_low_hz : 1;
+
+               /**
+                * Reserved bit 9-31
+                */
+               uint32_t reserved_9_31 : 23;
        } bitfields;
 
        uint32_t u32All;
@@ -3644,6 +3704,8 @@ enum dmub_cmd_replay_general_subtype {
         */
        REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP,
        REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION,
+       REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS,
+       REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE,
 };
 
 /**