drm/amdgpu: Clear overflow for SRIOV

For VF, it doesn't have the permission to clear overflow, clear the bit
by reset.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index 901f8b12c672d14ddc10484d2fa6418af767b68a..30f16968b5788691ee403c93dd6c3c696cef1985 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -25,6 +25,7 @@
 
 #include "amdgpu.h"
 #include "amdgpu_ih.h"
+#include "amdgpu_reset.h"
 
 /**
  * amdgpu_ih_ring_init - initialize the IH state
@@ -227,13 +228,23 @@ restart_ih:
                ih->rptr &= ih->ptr_mask;
        }
 
-       amdgpu_ih_set_rptr(adev, ih);
+       if (!ih->overflow)
+               amdgpu_ih_set_rptr(adev, ih);
+
        wake_up_all(&ih->wait_process);
 
        /* make sure wptr hasn't changed while processing */
        wptr = amdgpu_ih_get_wptr(adev, ih);
        if (wptr != ih->rptr)
-               goto restart_ih;
+               if (!ih->overflow)
+                       goto restart_ih;
+
+       if (ih->overflow)
+               if (amdgpu_sriov_runtime(adev))
+                       WARN_ONCE(!amdgpu_reset_domain_schedule(adev->reset_domain,
+                                  &adev->virt.flr_work),
+                                 "Failed to queue work! at %s",
+                                 __func__);
 
        return IRQ_HANDLED;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index b0a88f92cd821d6546c05361128dc005b562214c..7f7ea046e2097a59e18af0835a8411caf37ee16f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -72,6 +72,7 @@ struct amdgpu_ih_ring {
        /* For waiting on IH processing at checkpoint. */
        wait_queue_head_t wait_process;
        uint64_t                processed_timestamp;
+       bool overflow;
 };
 
 /* return true if time stamp t2 is after t1 with 48bit wrap around */

diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
index eb4185dcbd1d40cb9dd421daaa318a7c3800979c..5900b560b7dee809d8f21e7846595c364d8413dd 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
@@ -349,6 +349,7 @@ static int ih_v6_0_irq_init(struct amdgpu_device *adev)
                        if (ret)
                                return ret;
                }
+               ih[i]->overflow = false;
        }
 
        /* update doorbell range for ih ring 0 */
@@ -446,7 +447,10 @@ static u32 ih_v6_0_get_wptr(struct amdgpu_device *adev,
        wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
        if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
                goto out;
-       wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
+       if (!amdgpu_sriov_vf(adev))
+               wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
+       else
+               ih->overflow = true;
 
        /* When a ring buffer overflow happen start parsing interrupt
         * from the last not overwritten vector (wptr + 32). Hopefully

diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
index faa0dd75dd6d507e67fe6b12d83c5668358c367c..85846fd08ce4deb01b69e62bbaf7fc9cdec040c9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
@@ -350,6 +350,7 @@ static int vega20_ih_irq_init(struct amdgpu_device *adev)
                        if (ret)
                                return ret;
                }
+               ih[i]->overflow = false;
        }
 
        if (!amdgpu_sriov_vf(adev))
@@ -437,7 +438,10 @@ static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
        if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
                goto out;
 
-       wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
+       if (!amdgpu_sriov_vf(adev))
+               wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
+       else
+               ih->overflow = true;
 
        /* When a ring buffer overflow happen start parsing interrupt
         * from the last not overwritten vector (wptr + 32). Hopefully