RISC-V: Support VLS unary floating-point patterns

Extend current VLA patterns with VLS modes.

Regression all passed.

gcc/ChangeLog:

	* config/riscv/autovec.md: Extend VLS modes.
	* config/riscv/vector.md: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/def.h: Add unary test.
	* gcc.target/riscv/rvv/autovec/vls/neg-2.c: New test.

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 769ef6daa368696cae047b54ce548f8dae16d0f6..75ed7ae4f2e5cbf9f738ba8ca743d5436b3851ac 100644 (file)
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1031,9 +1031,9 @@
 ;; - vfneg.v/vfabs.v
 ;; -------------------------------------------------------------------------------
 (define_insn_and_split "<optab><mode>2"
-  [(set (match_operand:VF 0 "register_operand")
-    (any_float_unop_nofrm:VF
-     (match_operand:VF 1 "register_operand")))]
+  [(set (match_operand:V_VLSF 0 "register_operand")
+    (any_float_unop_nofrm:V_VLSF
+     (match_operand:V_VLSF 1 "register_operand")))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
   "&& 1"
@@ -1052,9 +1052,9 @@
 ;; - vfsqrt.v
 ;; -------------------------------------------------------------------------------
 (define_insn_and_split "<optab><mode>2"
-  [(set (match_operand:VF 0 "register_operand")
-    (any_float_unop:VF
-     (match_operand:VF 1 "register_operand")))]
+  [(set (match_operand:V_VLSF 0 "register_operand")
+    (any_float_unop:V_VLSF
+     (match_operand:V_VLSF 1 "register_operand")))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
   "&& 1"

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index f7f37da692ada67e119c6bdf33bfbdeb8dd808b3..f66ffebba247219ee22953b9fb8b188d6cb157aa 100644 (file)
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -6756,8 +6756,8 @@
 ;; -------------------------------------------------------------------------------
 
 (define_insn "@pred_<optab><mode>"
-  [(set (match_operand:VF 0 "register_operand"           "=vd, vd, vr, vr")
-       (if_then_else:VF
+  [(set (match_operand:V_VLSF 0 "register_operand"           "=vd, vd, vr, vr")
+       (if_then_else:V_VLSF
          (unspec:<VM>
            [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
             (match_operand 4 "vector_length_operand"    " rK, rK, rK, rK")
@@ -6768,9 +6768,9 @@
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)
             (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
-         (any_float_unop:VF
-           (match_operand:VF 3 "register_operand"       " vr, vr, vr, vr"))
-         (match_operand:VF 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
+         (any_float_unop:V_VLSF
+           (match_operand:V_VLSF 3 "register_operand"       " vr, vr, vr, vr"))
+         (match_operand:V_VLSF 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "vf<insn>.v\t%0,%3%p1"
   [(set_attr "type" "<float_insn_type>")
@@ -6783,8 +6783,8 @@
        (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
 
 (define_insn "@pred_<optab><mode>"
-  [(set (match_operand:VF 0 "register_operand"           "=vd, vd, vr, vr")
-       (if_then_else:VF
+  [(set (match_operand:V_VLSF 0 "register_operand"           "=vd, vd, vr, vr")
+       (if_then_else:V_VLSF
          (unspec:<VM>
            [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
             (match_operand 4 "vector_length_operand"    " rK, rK, rK, rK")
@@ -6793,9 +6793,9 @@
             (match_operand 7 "const_int_operand"        "  i,  i,  i,  i")
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-         (any_float_unop_nofrm:VF
-           (match_operand:VF 3 "register_operand"       " vr, vr, vr, vr"))
-         (match_operand:VF 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
+         (any_float_unop_nofrm:V_VLSF
+           (match_operand:V_VLSF 3 "register_operand"       " vr, vr, vr, vr"))
+         (match_operand:V_VLSF 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "vf<insn>.v\t%0,%3%p1"
   [(set_attr "type" "<float_insn_type>")

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 5df90704885088e40e07b3566e8b9b6a54bc4c7d..d7b721b4e3e42cd3d4fd69b6e48fccb182bc4edf 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -1,4 +1,5 @@
 #include <stdint-gcc.h>
+#include <math.h>
 
 typedef int8_t v1qi __attribute__ ((vector_size (1)));
 typedef int8_t v2qi __attribute__ ((vector_size (2)));
@@ -210,7 +211,7 @@ typedef double v512df __attribute__ ((vector_size (4096)));
   PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b)                    \
   {                                                                            \
     for (int i = 0; i < NUM; ++i)                                              \
-      a[i] = OP b[i];                                                          \
+      a[i] = OP (b[i]);                                                        \
   }
 
 #define DEF_CALL_VV(PREFIX, NUM, TYPE, CALL)                                   \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
new file mode 100644 (file)
index 0000000..c2ab009
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_OP_V (neg, 2, _Float16, -)
+DEF_OP_V (neg, 4, _Float16, -)
+DEF_OP_V (neg, 8, _Float16, -)
+DEF_OP_V (neg, 16, _Float16, -)
+DEF_OP_V (neg, 32, _Float16, -)
+DEF_OP_V (neg, 64, _Float16, -)
+DEF_OP_V (neg, 128, _Float16, -)
+DEF_OP_V (neg, 256, _Float16, -)
+DEF_OP_V (neg, 512, _Float16, -)
+DEF_OP_V (neg, 1024, _Float16, -)
+DEF_OP_V (neg, 2048, _Float16, -)
+
+DEF_OP_V (neg, 2, float, -)
+DEF_OP_V (neg, 4, float, -)
+DEF_OP_V (neg, 8, float, -)
+DEF_OP_V (neg, 16, float, -)
+DEF_OP_V (neg, 32, float, -)
+DEF_OP_V (neg, 64, float, -)
+DEF_OP_V (neg, 128, float, -)
+DEF_OP_V (neg, 256, float, -)
+DEF_OP_V (neg, 512, float, -)
+DEF_OP_V (neg, 1024, float, -)
+
+DEF_OP_V (neg, 2, double, -)
+DEF_OP_V (neg, 4, double, -)
+DEF_OP_V (neg, 8, double, -)
+DEF_OP_V (neg, 16, double, -)
+DEF_OP_V (neg, 32, double, -)
+DEF_OP_V (neg, 64, double, -)
+DEF_OP_V (neg, 128, double, -)
+DEF_OP_V (neg, 256, double, -)
+DEF_OP_V (neg, 512, double, -)
+
+/* { dg-final { scan-assembler-times {vfneg\.v\s+v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */