Merge tag 'v6.16' into x86/cpu, to resolve conflict

Resolve overlapping context conflict between this upstream fix:

  d8010d4ba43e ("x86/bugs: Add a Transient Scheduler Attacks mitigation")

And this pending commit in tip:x86/cpu:

  65f55a301766 ("x86/CPU/AMD: Add CPUID faulting support")

  Conflicts:
	arch/x86/kernel/cpu/amd.c

Signed-off-by: Ingo Molnar <mingo@kernel.org>

diff --cc arch/x86/include/asm/cpufeatures.h
index b78af55aa22e28d515dc985541f39bed948e4ce1,286d509f9363bc069587aae29762ad7051059787..602957dd2609ce4f533bf78e431662138b393aec
--- 1/arch/x86/include/asm/cpufeatures.h
--- 2/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@@ -456,8 -456,8 +456,9 @@@
  #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* No Nested Data Breakpoints */
  #define X86_FEATURE_WRMSR_XX_BASE_NS  (20*32+ 1) /* WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing */
  #define X86_FEATURE_LFENCE_RDTSC      (20*32+ 2) /* LFENCE always serializing / synchronizes RDTSC */
+ #define X86_FEATURE_VERW_CLEAR                (20*32+ 5) /* The memory form of VERW mitigates TSA */
  #define X86_FEATURE_NULL_SEL_CLR_BASE (20*32+ 6) /* Null Selector Clears Base */
 +
  #define X86_FEATURE_AUTOIBRS          (20*32+ 8) /* Automatic IBRS */
  #define X86_FEATURE_NO_SMM_CTL_MSR    (20*32+ 9) /* SMM_CTL MSR is not present */
  

diff --cc arch/x86/include/asm/msr-index.h
Simple merge

diff --cc arch/x86/kernel/cpu/amd.c
index 50f88fe51816556a99dcca62c511e24c420b15d3,329ee185d8ccafb8f613a07093b294a92b63ce56..a5ece6ebe8a74a706bf3e98e1e99603c2a655c3c
--- 1/arch/x86/kernel/cpu/amd.c
--- 2/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@@ -489,10 -530,9 +530,11 @@@ static void bsp_init_amd(struct cpuinfo
        }
  
        bsp_determine_snp(c);
 -
+       tsa_init(c);
  
 +      if (cpu_has(c, X86_FEATURE_GP_ON_USER_CPUID))
 +              setup_force_cpu_cap(X86_FEATURE_CPUID_FAULT);
 +
        return;
  
  warn:

diff --cc arch/x86/kernel/process.c
Simple merge