u32 size;
};
+struct orion_child_options {
+ struct orion_direct_acc direct_access;
+};
+
struct orion_spi {
struct spi_master *master;
void __iomem *base;
const struct orion_spi_dev *devdata;
int unused_hw_gpio;
- struct orion_direct_acc direct_access[ORION_NUM_CHIPSELECTS];
+ struct orion_child_options child[ORION_NUM_CHIPSELECTS];
};
static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
* Use SPI direct write mode if base address is available. Otherwise
* fall back to PIO mode for this transfer.
*/
- if ((orion_spi->direct_access[cs].vaddr) && (xfer->tx_buf) &&
+ if ((orion_spi->child[cs].direct_access.vaddr) && (xfer->tx_buf) &&
(word_len == 8)) {
unsigned int cnt = count / 4;
unsigned int rem = count % 4;
* Send the TX-data to the SPI device via the direct
* mapped address window
*/
- iowrite32_rep(orion_spi->direct_access[cs].vaddr,
+ iowrite32_rep(orion_spi->child[cs].direct_access.vaddr,
xfer->tx_buf, cnt);
if (rem) {
u32 *buf = (u32 *)xfer->tx_buf;
- iowrite8_rep(orion_spi->direct_access[cs].vaddr,
+ iowrite8_rep(orion_spi->child[cs].direct_access.vaddr,
&buf[cnt], rem);
}
* This needs to get extended for the direct SPI-NOR / SPI-NAND
* support, once this gets implemented.
*/
- spi->direct_access[cs].vaddr = devm_ioremap(&pdev->dev,
+ spi->child[cs].direct_access.vaddr = devm_ioremap(&pdev->dev,
r->start,
PAGE_SIZE);
- if (!spi->direct_access[cs].vaddr) {
+ if (!spi->child[cs].direct_access.vaddr) {
status = -ENOMEM;
goto out_rel_axi_clk;
}
- spi->direct_access[cs].size = PAGE_SIZE;
+ spi->child[cs].direct_access.size = PAGE_SIZE;
dev_info(&pdev->dev, "CS%d configured for direct access\n", cs);
}