--- /dev/null
+From bd903afeb504db5655a45bb4cf86f38be5b1bf62 Mon Sep 17 00:00:00 2001
+From: Song Liu <songliubraving@fb.com>
+Date: Mon, 5 Mar 2018 21:55:04 -0800
+Subject: perf/core: Fix ctx_event_type in ctx_resched()
+
+From: Song Liu <songliubraving@fb.com>
+
+commit bd903afeb504db5655a45bb4cf86f38be5b1bf62 upstream.
+
+In ctx_resched(), EVENT_FLEXIBLE should be sched_out when EVENT_PINNED is
+added. However, ctx_resched() calculates ctx_event_type before checking
+this condition. As a result, pinned events will NOT get higher priority
+than flexible events.
+
+The following shows this issue on an Intel CPU (where ref-cycles can
+only use one hardware counter).
+
+ 1. First start:
+ perf stat -C 0 -e ref-cycles -I 1000
+ 2. Then, in the second console, run:
+ perf stat -C 0 -e ref-cycles:D -I 1000
+
+The second perf uses pinned events, which is expected to have higher
+priority. However, because it failed in ctx_resched(). It is never
+run.
+
+This patch fixes this by calculating ctx_event_type after re-evaluating
+event_type.
+
+Reported-by: Ephraim Park <ephiepark@fb.com>
+Signed-off-by: Song Liu <songliubraving@fb.com>
+Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Cc: <jolsa@redhat.com>
+Cc: <kernel-team@fb.com>
+Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
+Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
+Cc: Jiri Olsa <jolsa@redhat.com>
+Cc: Linus Torvalds <torvalds@linux-foundation.org>
+Cc: Stephane Eranian <eranian@google.com>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Vince Weaver <vincent.weaver@maine.edu>
+Fixes: 487f05e18aa4 ("perf/core: Optimize event rescheduling on active contexts")
+Link: http://lkml.kernel.org/r/20180306055504.3283731-1-songliubraving@fb.com
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ kernel/events/core.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/kernel/events/core.c
++++ b/kernel/events/core.c
+@@ -2322,7 +2322,7 @@ static void ctx_resched(struct perf_cpu_
+ struct perf_event_context *task_ctx,
+ enum event_type_t event_type)
+ {
+- enum event_type_t ctx_event_type = event_type & EVENT_ALL;
++ enum event_type_t ctx_event_type;
+ bool cpu_event = !!(event_type & EVENT_CPU);
+
+ /*
+@@ -2332,6 +2332,8 @@ static void ctx_resched(struct perf_cpu_
+ if (event_type & EVENT_PINNED)
+ event_type |= EVENT_FLEXIBLE;
+
++ ctx_event_type = event_type & EVENT_ALL;
++
+ perf_pmu_disable(cpuctx->ctx.pmu);
+ if (task_ctx)
+ task_ctx_sched_out(cpuctx, task_ctx, event_type);
--- /dev/null
+From 40c21898ba5372c14ef71717040529794a91ccc2 Mon Sep 17 00:00:00 2001
+From: Ilya Pronin <ipronin@twitter.com>
+Date: Mon, 5 Mar 2018 22:43:53 -0800
+Subject: perf stat: Fix CVS output format for non-supported counters
+
+From: Ilya Pronin <ipronin@twitter.com>
+
+commit 40c21898ba5372c14ef71717040529794a91ccc2 upstream.
+
+When printing stats in CSV mode, 'perf stat' appends extra separators
+when a counter is not supported:
+
+<not supported>,,L1-dcache-store-misses,mesos/bd442f34-2b4a-47df-b966-9b281f9f56fc,0,100.00,,,,
+
+Which causes a failure when parsing fields. The numbers of separators
+should be the same for each line, no matter if the counter is or not
+supported.
+
+Signed-off-by: Ilya Pronin <ipronin@twitter.com>
+Acked-by: Jiri Olsa <jolsa@redhat.com>
+Cc: Andi Kleen <ak@linux.intel.com>
+Link: http://lkml.kernel.org/r/20180306064353.31930-1-xiyou.wangcong@gmail.com
+Fixes: 92a61f6412d3 ("perf stat: Implement CSV metrics output")
+Signed-off-by: Cong Wang <xiyou.wangcong@gmail.com>
+Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ tools/perf/builtin-stat.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/tools/perf/builtin-stat.c
++++ b/tools/perf/builtin-stat.c
+@@ -922,7 +922,7 @@ static void print_metric_csv(void *ctx,
+ char buf[64], *vals, *ends;
+
+ if (unit == NULL || fmt == NULL) {
+- fprintf(out, "%s%s%s%s", csv_sep, csv_sep, csv_sep, csv_sep);
++ fprintf(out, "%s%s", csv_sep, csv_sep);
+ return;
+ }
+ snprintf(buf, sizeof(buf), fmt, val);
--- /dev/null
+From e5ea9b54a055619160bbfe527ebb7d7191823d66 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Sat, 17 Mar 2018 14:52:16 +0300
+Subject: perf/x86/intel: Don't accidentally clear high bits in bdw_limit_period()
+
+From: Dan Carpenter <dan.carpenter@oracle.com>
+
+commit e5ea9b54a055619160bbfe527ebb7d7191823d66 upstream.
+
+We intended to clear the lowest 6 bits but because of a type bug we
+clear the high 32 bits as well. Andi says that periods are rarely more
+than U32_MAX so this bug probably doesn't have a huge runtime impact.
+
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
+Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
+Cc: H. Peter Anvin <hpa@zytor.com>
+Cc: Jiri Olsa <jolsa@redhat.com>
+Cc: Kan Liang <kan.liang@linux.intel.com>
+Cc: Linus Torvalds <torvalds@linux-foundation.org>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
+Cc: Stephane Eranian <eranian@google.com>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Vince Weaver <vincent.weaver@maine.edu>
+Fixes: 294fe0f52a44 ("perf/x86/intel: Add INST_RETIRED.ALL workarounds")
+Link: http://lkml.kernel.org/r/20180317115216.GB4035@mwanda
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/events/intel/core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/x86/events/intel/core.c
++++ b/arch/x86/events/intel/core.c
+@@ -3194,7 +3194,7 @@ static unsigned bdw_limit_period(struct
+ X86_CONFIG(.event=0xc0, .umask=0x01)) {
+ if (left < 128)
+ left = 128;
+- left &= ~0x3fu;
++ left &= ~0x3fULL;
+ }
+ return left;
+ }
--- /dev/null
+From 320b0651f32b830add6497fcdcfdcb6ae8c7b8a0 Mon Sep 17 00:00:00 2001
+From: Kan Liang <kan.liang@linux.intel.com>
+Date: Tue, 13 Mar 2018 11:51:34 -0700
+Subject: perf/x86/intel/uncore: Fix multi-domain PCI CHA enumeration bug on Skylake servers
+
+From: Kan Liang <kan.liang@linux.intel.com>
+
+commit 320b0651f32b830add6497fcdcfdcb6ae8c7b8a0 upstream.
+
+The number of CHAs is miscalculated on multi-domain PCI Skylake server systems,
+resulting in an uncore driver initialization error.
+
+Gary Kroening explains:
+
+ "For systems with a single PCI segment, it is sufficient to look for the
+ bus number to change in order to determine that all of the CHa's have
+ been counted for a single socket.
+
+ However, for multi PCI segment systems, each socket is given a new
+ segment and the bus number does NOT change. So looking only for the
+ bus number to change ends up counting all of the CHa's on all sockets
+ in the system. This leads to writing CPU MSRs beyond a valid range and
+ causes an error in ivbep_uncore_msr_init_box()."
+
+To fix this bug, query the number of CHAs from the CAPID6 register:
+it should read bits 27:0 in the CAPID6 register located at
+Device 30, Function 3, Offset 0x9C. These 28 bits form a bit vector
+of available LLC slices and the CHAs that manage those slices.
+
+Reported-by: Kroening, Gary <gary.kroening@hpe.com>
+Tested-by: Kroening, Gary <gary.kroening@hpe.com>
+Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
+Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
+Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
+Cc: Jiri Olsa <jolsa@redhat.com>
+Cc: Linus Torvalds <torvalds@linux-foundation.org>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: Stephane Eranian <eranian@google.com>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Vince Weaver <vincent.weaver@maine.edu>
+Cc: abanman@hpe.com
+Cc: dimitri.sivanich@hpe.com
+Cc: hpa@zytor.com
+Cc: mike.travis@hpe.com
+Cc: russ.anderson@hpe.com
+Fixes: cd34cd97b7b4 ("perf/x86/intel/uncore: Add Skylake server uncore support")
+Link: http://lkml.kernel.org/r/1520967094-13219-1-git-send-email-kan.liang@linux.intel.com
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/events/intel/uncore_snbep.c | 31 +++++++++++++++++--------------
+ 1 file changed, 17 insertions(+), 14 deletions(-)
+
+--- a/arch/x86/events/intel/uncore_snbep.c
++++ b/arch/x86/events/intel/uncore_snbep.c
+@@ -3554,24 +3554,27 @@ static struct intel_uncore_type *skx_msr
+ NULL,
+ };
+
++/*
++ * To determine the number of CHAs, it should read bits 27:0 in the CAPID6
++ * register which located at Device 30, Function 3, Offset 0x9C. PCI ID 0x2083.
++ */
++#define SKX_CAPID6 0x9c
++#define SKX_CHA_BIT_MASK GENMASK(27, 0)
++
+ static int skx_count_chabox(void)
+ {
+- struct pci_dev *chabox_dev = NULL;
+- int bus, count = 0;
++ struct pci_dev *dev = NULL;
++ u32 val = 0;
+
+- while (1) {
+- chabox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x208d, chabox_dev);
+- if (!chabox_dev)
+- break;
+- if (count == 0)
+- bus = chabox_dev->bus->number;
+- if (bus != chabox_dev->bus->number)
+- break;
+- count++;
+- }
++ dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2083, dev);
++ if (!dev)
++ goto out;
+
+- pci_dev_put(chabox_dev);
+- return count;
++ pci_read_config_dword(dev, SKX_CAPID6, &val);
++ val &= SKX_CHA_BIT_MASK;
++out:
++ pci_dev_put(dev);
++ return hweight32(val);
+ }
+
+ void skx_uncore_cpu_init(void)
--- /dev/null
+From 317660940fd9dddd3201c2f92e25c27902c753fa Mon Sep 17 00:00:00 2001
+From: Kan Liang <kan.liang@linux.intel.com>
+Date: Fri, 2 Mar 2018 07:22:30 -0800
+Subject: perf/x86/intel/uncore: Fix Skylake UPI event format
+
+From: Kan Liang <kan.liang@linux.intel.com>
+
+commit 317660940fd9dddd3201c2f92e25c27902c753fa upstream.
+
+There is no event extension (bit 21) for SKX UPI, so
+use 'event' instead of 'event_ext'.
+
+Reported-by: Stephane Eranian <eranian@google.com>
+Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
+Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
+Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
+Cc: Jiri Olsa <jolsa@redhat.com>
+Cc: Linus Torvalds <torvalds@linux-foundation.org>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Vince Weaver <vincent.weaver@maine.edu>
+Fixes: cd34cd97b7b4 ("perf/x86/intel/uncore: Add Skylake server uncore support")
+Link: http://lkml.kernel.org/r/1520004150-4855-1-git-send-email-kan.liang@linux.intel.com
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/events/intel/uncore_snbep.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/x86/events/intel/uncore_snbep.c
++++ b/arch/x86/events/intel/uncore_snbep.c
+@@ -3598,7 +3598,7 @@ static struct intel_uncore_type skx_unco
+ };
+
+ static struct attribute *skx_upi_uncore_formats_attr[] = {
+- &format_attr_event_ext.attr,
++ &format_attr_event.attr,
+ &format_attr_umask_ext.attr,
+ &format_attr_edge.attr,
+ &format_attr_inv.attr,
x86-build-64-force-the-linker-to-use-2mb-page-size.patch
x86-boot-64-verify-alignment-of-the-load-segment.patch
drm-syncobj-stop-reusing-the-same-struct-file-for-all-syncobj-fd.patch
+perf-x86-intel-uncore-fix-skylake-upi-event-format.patch
+perf-stat-fix-cvs-output-format-for-non-supported-counters.patch
+perf-core-fix-ctx_event_type-in-ctx_resched.patch
+perf-x86-intel-don-t-accidentally-clear-high-bits-in-bdw_limit_period.patch
+perf-x86-intel-uncore-fix-multi-domain-pci-cha-enumeration-bug-on-skylake-servers.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
