cxl/pci: Remove duplicated implementation of waiting for memory_info_valid

commit ce17ad0d5498 ("cxl: Wait Memory_Info_Valid before access memory
related info") added another implementation, which is
cxl_dvsec_mem_range_valid(), of waiting for memory_info_valid without
realizing it duplicated wait_for_valid(). Remove wait_for_valid() and
retain cxl_dvsec_mem_range_valid() as the former is hardcoded to check
only the Memory_Info_Valid bit of DVSEC range 1, while the latter allows
for selection between DVSEC range 1 or 2 via parameter.

Suggested-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Yanfei Xu <yanfei.xu@intel.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20240828084231.1378789-3-yanfei.xu@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 075a2b2d2ea0e23c442133637e6a392a42dd43cc..37e537e50b3467cd3fb419f35ec344baa0ad8b0c 100644 (file)
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -211,37 +211,6 @@ int cxl_await_media_ready(struct cxl_dev_state *cxlds)
 }
 EXPORT_SYMBOL_NS_GPL(cxl_await_media_ready, CXL);
 
-static int wait_for_valid(struct pci_dev *pdev, int d)
-{
-       u32 val;
-       int rc;
-
-       /*
-        * Memory_Info_Valid: When set, indicates that the CXL Range 1 Size high
-        * and Size Low registers are valid. Must be set within 1 second of
-        * deassertion of reset to CXL device. Likely it is already set by the
-        * time this runs, but otherwise give a 1.5 second timeout in case of
-        * clock skew.
-        */
-       rc = pci_read_config_dword(pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(0), &val);
-       if (rc)
-               return rc;
-
-       if (val & CXL_DVSEC_MEM_INFO_VALID)
-               return 0;
-
-       msleep(1500);
-
-       rc = pci_read_config_dword(pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(0), &val);
-       if (rc)
-               return rc;
-
-       if (val & CXL_DVSEC_MEM_INFO_VALID)
-               return 0;
-
-       return -ETIMEDOUT;
-}
-
 static int cxl_set_mem_enable(struct cxl_dev_state *cxlds, u16 val)
 {
        struct pci_dev *pdev = to_pci_dev(cxlds->dev);
@@ -322,11 +291,13 @@ static int devm_cxl_enable_hdm(struct device *host, struct cxl_hdm *cxlhdm)
        return devm_add_action_or_reset(host, disable_hdm, cxlhdm);
 }
 
-int cxl_dvsec_rr_decode(struct device *dev, int d,
+int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port,
                        struct cxl_endpoint_dvsec_info *info)
 {
        struct pci_dev *pdev = to_pci_dev(dev);
+       struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
        int hdm_count, rc, i, ranges = 0;
+       int d = cxlds->cxl_dvsec;
        u16 cap, ctrl;
 
        if (!d) {
@@ -353,11 +324,9 @@ int cxl_dvsec_rr_decode(struct device *dev, int d,
        if (!hdm_count || hdm_count > 2)
                return -EINVAL;
 
-       rc = wait_for_valid(pdev, d);
-       if (rc) {
-               dev_dbg(dev, "Failure awaiting MEM_INFO_VALID (%d)\n", rc);
+       rc = cxl_dvsec_mem_range_valid(cxlds, 0);
+       if (rc)
                return rc;
-       }
 
        /*
         * The current DVSEC values are moot if the memory capability is

diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 2890f7e2aad5dcb0215cd0d83a6c15fcf9a62804..0fc96f8bf15c5e0ad57c64c0f88a97d901db06c6 100644 (file)
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -811,7 +811,7 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
 int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm,
                                struct cxl_endpoint_dvsec_info *info);
 int devm_cxl_add_passthrough_decoder(struct cxl_port *port);
-int cxl_dvsec_rr_decode(struct device *dev, int dvsec,
+int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port,
                        struct cxl_endpoint_dvsec_info *info);
 
 bool is_cxl_region(struct device *dev);

diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
index d7d5d982ce69f3c3c2a5eeb6b9d0fc39e910656e..861dde65768fe383d3ccbb49ffd31fb29aeb42e9 100644 (file)
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@ -98,7 +98,7 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
        struct cxl_port *root;
        int rc;
 
-       rc = cxl_dvsec_rr_decode(cxlds->dev, cxlds->cxl_dvsec, &info);
+       rc = cxl_dvsec_rr_decode(cxlds->dev, port, &info);
        if (rc < 0)
                return rc;
 

diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c
index bbd7d938156d91408f2d7757269e5d0af2837999..f4ce96cc11d4b01689867c6b9c8c0b5efd5ec18b 100644 (file)
--- a/tools/testing/cxl/test/mock.c
+++ b/tools/testing/cxl/test/mock.c
@@ -228,7 +228,7 @@ int __wrap_cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
 }
 EXPORT_SYMBOL_NS_GPL(__wrap_cxl_hdm_decode_init, CXL);
 
-int __wrap_cxl_dvsec_rr_decode(struct device *dev, int dvsec,
+int __wrap_cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port,
                               struct cxl_endpoint_dvsec_info *info)
 {
        int rc = 0, index;
@@ -237,7 +237,7 @@ int __wrap_cxl_dvsec_rr_decode(struct device *dev, int dvsec,
        if (ops && ops->is_mock_dev(dev))
                rc = 0;
        else
-               rc = cxl_dvsec_rr_decode(dev, dvsec, info);
+               rc = cxl_dvsec_rr_decode(dev, port, info);
        put_cxl_mock_ops(index);
 
        return rc;