drm/amd/amdgpu: change the config of cgcg on gfx12

change the config of cgcg on gfx12

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.12.x

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index c1772f44b1d7476261ba7500a22a62537d01b95f..2523221a2519d3c0f694cdb69639e6160d8b50b0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -4021,17 +4021,6 @@ static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
 
                if (def != data)
                        WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
-
-               data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
-               data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
-               WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
-
-               /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
-               if (adev->sdma.num_instances > 1) {
-                       data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
-                       data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
-                       WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
-               }
        }
 }