5.2-stable patches

added patches:
	drm-i915-gvt-fix-incorrect-cache-entry-for-guest-page-mapping.patch
	drm-i915-perf-fix-icl-perf-register-offsets.patch

diff --git a/queue-5.2/drm-i915-gvt-fix-incorrect-cache-entry-for-guest-page-mapping.patch b/queue-5.2/drm-i915-gvt-fix-incorrect-cache-entry-for-guest-page-mapping.patch
new file mode 100644 (file)
index 0000000..058aa8b
--- /dev/null
+++ b/queue-5.2/drm-i915-gvt-fix-incorrect-cache-entry-for-guest-page-mapping.patch
@@ -0,0 +1,49 @@
+From 7366aeb77cd840f3edea02c65065d40affaa7f45 Mon Sep 17 00:00:00 2001
+From: Xiaolin Zhang <xiaolin.zhang@intel.com>
+Date: Thu, 18 Jul 2019 01:10:24 +0800
+Subject: drm/i915/gvt: fix incorrect cache entry for guest page mapping
+
+From: Xiaolin Zhang <xiaolin.zhang@intel.com>
+
+commit 7366aeb77cd840f3edea02c65065d40affaa7f45 upstream.
+
+GPU hang observed during the guest OCL conformance test which is caused
+by THP GTT feature used durning the test.
+
+It was observed the same GFN with different size (4K and 2M) requested
+from the guest in GVT. So during the guest page dma map stage, it is
+required to unmap first with orginal size and then remap again with
+requested size.
+
+Fixes: b901b252b6cf ("drm/i915/gvt: Add 2M huge gtt support")
+Cc: stable@vger.kernel.org
+Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
+Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
+Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/gvt/kvmgt.c |   12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
++++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
+@@ -1911,6 +1911,18 @@ static int kvmgt_dma_map_guest_page(unsi
+               ret = __gvt_cache_add(info->vgpu, gfn, *dma_addr, size);
+               if (ret)
+                       goto err_unmap;
++      } else if (entry->size != size) {
++              /* the same gfn with different size: unmap and re-map */
++              gvt_dma_unmap_page(vgpu, gfn, entry->dma_addr, entry->size);
++              __gvt_cache_remove_entry(vgpu, entry);
++
++              ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size);
++              if (ret)
++                      goto err_unlock;
++
++              ret = __gvt_cache_add(info->vgpu, gfn, *dma_addr, size);
++              if (ret)
++                      goto err_unmap;
+       } else {
+               kref_get(&entry->ref);
+               *dma_addr = entry->dma_addr;

diff --git a/queue-5.2/drm-i915-perf-fix-icl-perf-register-offsets.patch b/queue-5.2/drm-i915-perf-fix-icl-perf-register-offsets.patch
new file mode 100644 (file)
index 0000000..d5c7740
--- /dev/null
+++ b/queue-5.2/drm-i915-perf-fix-icl-perf-register-offsets.patch
@@ -0,0 +1,45 @@
+From 95eef14cdad150fed43147bcd4f29eea3d0a3f03 Mon Sep 17 00:00:00 2001
+From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
+Date: Mon, 10 Jun 2019 11:19:14 +0300
+Subject: drm/i915/perf: fix ICL perf register offsets
+
+From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
+
+commit 95eef14cdad150fed43147bcd4f29eea3d0a3f03 upstream.
+
+We got the wrong offsets (could they have changed?). New values were
+computed off an error state by looking up the register offset in the
+context image as written by the HW.
+
+Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
+Fixes: 1de401c08fa805 ("drm/i915/perf: enable perf support on ICL")
+Cc: <stable@vger.kernel.org> # v4.18+
+Acked-by: Kenneth Graunke <kenneth@whitecape.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190610081914.25428-1-lionel.g.landwerlin@intel.com
+(cherry picked from commit 8dcfdfb4501012a8d36d2157dc73925715f2befb)
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/i915_perf.c |   10 +++++++---
+ 1 file changed, 7 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_perf.c
++++ b/drivers/gpu/drm/i915/i915_perf.c
+@@ -3457,9 +3457,13 @@ void i915_perf_init(struct drm_i915_priv
+                       dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set;
+                       dev_priv->perf.oa.ops.disable_metric_set = gen10_disable_metric_set;
+ 
+-                      dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
+-                      dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;
+-
++                      if (IS_GEN(dev_priv, 10)) {
++                              dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
++                              dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;
++                      } else {
++                              dev_priv->perf.oa.ctx_oactxctrl_offset = 0x124;
++                              dev_priv->perf.oa.ctx_flexeu0_offset = 0x78e;
++                      }
+                       dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
+               }
+       }

diff --git a/queue-5.2/series b/queue-5.2/series
index 461988af10e27a4645d71f4fd401625b972537ac..15bdd70c095b2f38fe26645cc7852603bccbdf7b 100644 (file)
--- a/queue-5.2/series
+++ b/queue-5.2/series
@@ -127,3 +127,5 @@ ib-mlx5-fix-rss-toeplitz-setup-to-be-aligned-with-the-hw-specification.patch
 ib-hfi1-check-for-error-on-call-to-alloc_rsm_map_table.patch
 ib-hfi1-drop-all-tid-rdma-read-resp-packets-after-r_next_psn.patch
 ib-hfi1-field-not-zero-ed-when-allocating-tid-flow-memory.patch
+drm-i915-perf-fix-icl-perf-register-offsets.patch
+drm-i915-gvt-fix-incorrect-cache-entry-for-guest-page-mapping.patch