drm/i915/xe2lpd: Update C20 algorithm to include tx_misc

There has been an update to the BSpec in which we need to set
tx_misc=0x5 field for C20 TX Context programming for HDMI TMDS for
Xe2_LPD and newer. That field is mapped to the bits 7:0 of
SRAM_GENERIC_<A/B>_TX_CNTX_CFG_1, which in turn translates to tx[1] of
our state struct. Update the algorithm to reflect this change.

v2:
  - Fix Bspec reference (Sai Teja)
  - Use struct intel_display instead of drm_i915_private. (Jani)
  - Use the correct bit width for C20_PHY_TX_MISC_MASK. (Jani)

Bspec: 74491
Cc: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com> #v1
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241023153352.144146-3-gustavo.sousa@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 21ebe128101285f3ecc62b9ab9c61b3f1a408c9d..7b724c157413f42c0c27f8452ad03960f40efadd 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2161,6 +2161,7 @@ static void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
 
 static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state)
 {
+       struct intel_display *display = to_intel_display(crtc_state);
        struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20;
        u64 datarate;
        u64 mpll_tx_clk_div;
@@ -2170,6 +2171,7 @@ static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state)
        u64 mpll_multiplier;
        u64 mpll_fracn_quot;
        u64 mpll_fracn_rem;
+       u16 tx_misc;
        u8  mpllb_ana_freq_vco;
        u8  mpll_div_multiplier;
 
@@ -2189,6 +2191,11 @@ static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state)
        mpll_div_multiplier = min_t(u8, div64_u64((vco_freq * 16 + (datarate >> 1)),
                                                  datarate), 255);
 
+       if (DISPLAY_VER(display) >= 20)
+               tx_misc = 0x5;
+       else
+               tx_misc = 0x0;
+
        if (vco_freq <= DATARATE_3000000000)
                mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_3;
        else if (vco_freq <= DATARATE_3500000000)
@@ -2200,7 +2207,7 @@ static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state)
 
        pll_state->clock        = crtc_state->port_clock;
        pll_state->tx[0]        = 0xbe88;
-       pll_state->tx[1]        = 0x9800;
+       pll_state->tx[1]        = 0x9800 | C20_PHY_TX_MISC(tx_misc);
        pll_state->tx[2]        = 0x0000;
        pll_state->cmn[0]       = 0x0500;
        pll_state->cmn[1]       = 0x0005;

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index ab3ae110b68f3f149e695b9b470c2d7005ffa3d2..fdce4152a7c951d2880d4887fcbbeebfc26704c8 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -280,6 +280,8 @@
 #define PHY_C20_B_TX_CNTX_CFG(i915, idx) \
                ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_TX_CNTX_CFG : _MTL_C20_B_TX_CNTX_CFG) - (idx))
 #define   C20_PHY_TX_RATE              REG_GENMASK(2, 0)
+#define   C20_PHY_TX_MISC_MASK         REG_GENMASK16(7, 0)
+#define   C20_PHY_TX_MISC(val)         REG_FIELD_PREP16(C20_PHY_TX_MISC_MASK, (val))
 
 #define PHY_C20_A_CMN_CNTX_CFG(i915, idx) \
                ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_CMN_CNTX_CFG : _MTL_C20_A_CMN_CNTX_CFG) - (idx))