net: stmmac: rk: use PHY_INTF_SEL_x constants

The values used in the xxx_GMAC_PHY_INTF_SEL_xxx() macros are the
phy_intf_sel values used for the dwmac core. Use these to define these
constants.

No change to produced code on aarch64.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Link: https://patch.msgid.link/E1vJbPB-0000000EBqV-27GS@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 4257cc1f66e9b86d50e671d906b38980a782ede4..49076ee00877b76c3fdccd76219a1c0ec8b16399 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -234,7 +234,7 @@ static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv,
 #define PX30_GRF_GMAC_CON1             0x0904
 
 /* PX30_GRF_GMAC_CON1 */
-#define PX30_GMAC_PHY_INTF_SEL_RMII    GRF_FIELD(6, 4, 4)
+#define PX30_GMAC_PHY_INTF_SEL_RMII    GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
 #define PX30_GMAC_SPEED_10M            GRF_CLR_BIT(2)
 #define PX30_GMAC_SPEED_100M           GRF_BIT(2)
 
@@ -290,8 +290,8 @@ static const struct rk_gmac_ops px30_ops = {
 #define RK3128_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
 
 /* RK3128_GRF_MAC_CON1 */
-#define RK3128_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, 1)
-#define RK3128_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(8, 6, 4)
+#define RK3128_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, PHY_INTF_SEL_RGMII)
+#define RK3128_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(8, 6, PHY_INTF_SEL_RMII)
 #define RK3128_GMAC_FLOW_CTRL          GRF_BIT(9)
 #define RK3128_GMAC_FLOW_CTRL_CLR      GRF_CLR_BIT(9)
 #define RK3128_GMAC_SPEED_10M          GRF_CLR_BIT(10)
@@ -353,8 +353,8 @@ static const struct rk_gmac_ops rk3128_ops = {
 #define RK3228_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
 
 /* RK3228_GRF_MAC_CON1 */
-#define RK3228_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1)
-#define RK3228_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(6, 4, 4)
+#define RK3228_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
+#define RK3228_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
 #define RK3228_GMAC_FLOW_CTRL          GRF_BIT(3)
 #define RK3228_GMAC_FLOW_CTRL_CLR      GRF_CLR_BIT(3)
 #define RK3228_GMAC_SPEED_10M          GRF_CLR_BIT(2)
@@ -432,8 +432,8 @@ static const struct rk_gmac_ops rk3228_ops = {
 #define RK3288_GRF_SOC_CON3    0x0250
 
 /*RK3288_GRF_SOC_CON1*/
-#define RK3288_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, 1)
-#define RK3288_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(8, 6, 4)
+#define RK3288_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, PHY_INTF_SEL_RGMII)
+#define RK3288_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(8, 6, PHY_INTF_SEL_RMII)
 #define RK3288_GMAC_FLOW_CTRL          GRF_BIT(9)
 #define RK3288_GMAC_FLOW_CTRL_CLR      GRF_CLR_BIT(9)
 #define RK3288_GMAC_SPEED_10M          GRF_CLR_BIT(10)
@@ -496,7 +496,7 @@ static const struct rk_gmac_ops rk3288_ops = {
 #define RK3308_GRF_MAC_CON0            0x04a0
 
 /* RK3308_GRF_MAC_CON0 */
-#define RK3308_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(4, 2, 4)
+#define RK3308_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(4, 2, PHY_INTF_SEL_RMII)
 #define RK3308_GMAC_FLOW_CTRL          GRF_BIT(3)
 #define RK3308_GMAC_FLOW_CTRL_CLR      GRF_CLR_BIT(3)
 #define RK3308_GMAC_SPEED_10M          GRF_CLR_BIT(0)
@@ -535,8 +535,8 @@ static const struct rk_gmac_ops rk3308_ops = {
 #define RK3328_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
 
 /* RK3328_GRF_MAC_CON1 */
-#define RK3328_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1)
-#define RK3328_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(6, 4, 4)
+#define RK3328_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
+#define RK3328_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
 #define RK3328_GMAC_FLOW_CTRL          GRF_BIT(3)
 #define RK3328_GMAC_FLOW_CTRL_CLR      GRF_CLR_BIT(3)
 #define RK3328_GMAC_SPEED_10M          GRF_CLR_BIT(2)
@@ -622,8 +622,8 @@ static const struct rk_gmac_ops rk3328_ops = {
 #define RK3366_GRF_SOC_CON7    0x041c
 
 /* RK3366_GRF_SOC_CON6 */
-#define RK3366_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, 1)
-#define RK3366_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(11, 9, 4)
+#define RK3366_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, PHY_INTF_SEL_RGMII)
+#define RK3366_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(11, 9, PHY_INTF_SEL_RMII)
 #define RK3366_GMAC_FLOW_CTRL          GRF_BIT(8)
 #define RK3366_GMAC_FLOW_CTRL_CLR      GRF_CLR_BIT(8)
 #define RK3366_GMAC_SPEED_10M          GRF_CLR_BIT(7)
@@ -687,8 +687,8 @@ static const struct rk_gmac_ops rk3366_ops = {
 #define RK3368_GRF_SOC_CON16   0x0440
 
 /* RK3368_GRF_SOC_CON15 */
-#define RK3368_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, 1)
-#define RK3368_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(11, 9, 4)
+#define RK3368_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, PHY_INTF_SEL_RGMII)
+#define RK3368_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(11, 9, PHY_INTF_SEL_RMII)
 #define RK3368_GMAC_FLOW_CTRL          GRF_BIT(8)
 #define RK3368_GMAC_FLOW_CTRL_CLR      GRF_CLR_BIT(8)
 #define RK3368_GMAC_SPEED_10M          GRF_CLR_BIT(7)
@@ -752,8 +752,8 @@ static const struct rk_gmac_ops rk3368_ops = {
 #define RK3399_GRF_SOC_CON6    0xc218
 
 /* RK3399_GRF_SOC_CON5 */
-#define RK3399_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, 1)
-#define RK3399_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(11, 9, 4)
+#define RK3399_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, PHY_INTF_SEL_RGMII)
+#define RK3399_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(11, 9, PHY_INTF_SEL_RMII)
 #define RK3399_GMAC_FLOW_CTRL          GRF_BIT(8)
 #define RK3399_GMAC_FLOW_CTRL_CLR      GRF_CLR_BIT(8)
 #define RK3399_GMAC_SPEED_10M          GRF_CLR_BIT(7)
@@ -1015,8 +1015,8 @@ static const struct rk_gmac_ops rk3528_ops = {
 #define RK3568_GRF_GMAC1_CON1          0x038c
 
 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
-#define RK3568_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1)
-#define RK3568_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(6, 4, 4)
+#define RK3568_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
+#define RK3568_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
 #define RK3568_GMAC_FLOW_CTRL                  GRF_BIT(3)
 #define RK3568_GMAC_FLOW_CTRL_CLR              GRF_CLR_BIT(3)
 #define RK3568_GMAC_RXCLK_DLY_ENABLE           GRF_BIT(1)
@@ -1209,9 +1209,9 @@ static const struct rk_gmac_ops rk3576_ops = {
 #define RK3588_GRF_CLK_CON1                    0X0070
 
 #define RK3588_GMAC_PHY_INTF_SEL_RGMII(id)     \
-       (GRF_FIELD(5, 3, 1) << ((id) * 6))
+       (GRF_FIELD(5, 3, PHY_INTF_SEL_RGMII) << ((id) * 6))
 #define RK3588_GMAC_PHY_INTF_SEL_RMII(id)      \
-       (GRF_FIELD(5, 3, 4) << ((id) * 6))
+       (GRF_FIELD(5, 3, PHY_INTF_SEL_RMII) << ((id) * 6))
 
 #define RK3588_GMAC_CLK_RMII_MODE(id)          GRF_BIT(5 * (id))
 #define RK3588_GMAC_CLK_RGMII_MODE(id)         GRF_CLR_BIT(5 * (id))
@@ -1328,7 +1328,7 @@ static const struct rk_gmac_ops rk3588_ops = {
 #define RV1108_GRF_GMAC_CON0           0X0900
 
 /* RV1108_GRF_GMAC_CON0 */
-#define RV1108_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(6, 4, 4)
+#define RV1108_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
 #define RV1108_GMAC_FLOW_CTRL          GRF_BIT(3)
 #define RV1108_GMAC_FLOW_CTRL_CLR      GRF_CLR_BIT(3)
 #define RV1108_GMAC_SPEED_10M          GRF_CLR_BIT(2)
@@ -1364,8 +1364,8 @@ static const struct rk_gmac_ops rv1108_ops = {
 #define RV1126_GRF_GMAC_CON2           0X0078
 
 /* RV1126_GRF_GMAC_CON0 */
-#define RV1126_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1)
-#define RV1126_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(6, 4, 4)
+#define RV1126_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
+#define RV1126_GMAC_PHY_INTF_SEL_RMII  GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
 #define RV1126_GMAC_FLOW_CTRL                  GRF_BIT(7)
 #define RV1126_GMAC_FLOW_CTRL_CLR              GRF_CLR_BIT(7)
 #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE                GRF_BIT(1)