+2003-03-26 Vladimir Makarov <vmakarov@redhat.com>
+
+ * config/rs6000/8540.md: New file.
+
+ * config/rs6000/{40x.md, 603.md, 6xx.md, 7450.md, 7xx.md, mpc.md,
+ power4.md, rios1.md, rios2.md, rs64.md}: Add mult_compare to
+ reservations for imul.
+
+ * config/rs6000/rs6000.md: Include 8540.md. Change
+ delayed_compare onto mult_compare for insns generating
+ multiplication.
+ (mult_compare, fpsimple, brinc, vecdiv, veccmpsimple, vecfdiv):
+ New type attribute values.
+
+ * config/rs6000/spe.md (*negsf2_gp, *abssf2_gpr): Use type
+ fpsimple instead of fp.
+ (*divsf3_gpr): Use type vecfdiv instead of fp.
+ (spe_evfsabs, spe_evfsnabs, spe_evfsneg): Use type vecsimple
+ instead of vecfloat.
+ (spe_evfsdive): Use type vecfdiv instead of vecfloat.
+ (spe_brinc): Use type brinc instead of veccomplex.
+ (spe_evaddw, spe_evaddiw): Use type vecsimple instead of
+ veccomplex.
+ (spe_evdivws, spe_evdivwu): Use type vecdiv instead of veccomplex.
+ (*movv2si_internal, *movv1di_internal, *movv4hi_internal,
+ *movv2sf_internal): Define type attribute values for all
+ alternatives.
+ (cmpsfeq_gpr, cmpsfgt_gpr, cmpsflt_gpr): Use type veccmp instead
+ of fpcompare.
+ (tstsfeq_gpr, tstsfgt_gpr, tstsflt_gpr): Use type veccmpsimple
+ instead of fpcompare.
+
2003-03-26 David Edelsohn <edelsohn@gnu.org>
* config/rs6000/power4.md: Allow delay between dispatch and
"iu_40x,nothing,bpu_40x")
(define_insn_reservation "ppc403-imul" 4
- (and (eq_attr "type" "imul,imul2,imul3")
+ (and (eq_attr "type" "imul,imul2,imul3,mult_compare")
(eq_attr "cpu" "ppc403"))
"iu_40x*4")
(define_insn_reservation "ppc405-imul" 5
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,mult_compare")
(eq_attr "cpu" "ppc405"))
"iu_40x*4")
; This takes 2 or 3 cycles
(define_insn_reservation "ppc603-imul" 3
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,mult_compare")
(eq_attr "cpu" "ppc603"))
"iu_603*2")
"iu1_6xx|iu2_6xx")
(define_insn_reservation "ppc604-imul" 4
- (and (eq_attr "type" "imul,imul2,imul3")
+ (and (eq_attr "type" "imul,imul2,imul3,mult_compare")
(eq_attr "cpu" "ppc604"))
"mciu_6xx*2")
(define_insn_reservation "ppc604e-imul" 2
- (and (eq_attr "type" "imul,imul2,imul3")
+ (and (eq_attr "type" "imul,imul2,imul3,mult_compare")
(eq_attr "cpu" "ppc604e"))
"mciu_6xx")
(define_insn_reservation "ppc620-imul" 5
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,mult_compare")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*3")
"ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
(define_insn_reservation "ppc7450-imul" 4
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,mult_compare")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,mciu_7450*2")
"ppc750_du,(iu1_7xx|iu2_7xx)")
(define_insn_reservation "ppc750-imul" 4
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,mult_compare")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx*4")
--- /dev/null
+;; Pipeline description for Motorola PowerPC 8540 processor.
+;; Copyright (C) 2003 Free Software Foundation, Inc.
+;;
+;; This file is part of GNU CC.
+;;
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+(define_automaton "ppc8540_most,ppc8540_long,ppc8540_retire")
+(define_cpu_unit "ppc8540_decode_0,ppc8540_decode_1" "ppc8540_most")
+(define_cpu_unit "ppc8540_issue_0,ppc8540_issue_1" "ppc8540_most")
+
+;; We could describe completion buffers slots in combination with the
+;; retirement units and the order of completion but the result
+;; automaton would behave in the same way because we can not describe
+;; real latency time with taking in order completion into account.
+;; Actually we could define the real latency time by querying reserved
+;; automaton units but the current scheduler uses latency time before
+;; issuing insns and making any reservations.
+;;
+;; So our description is aimed to achieve a insn schedule in which the
+;; insns would not wait in the completion buffer.
+(define_cpu_unit "ppc8540_retire_0,ppc8540_retire_1" "ppc8540_retire")
+
+;; Branch unit:
+(define_cpu_unit "ppc8540_bu" "ppc8540_most")
+
+;; SIU:
+(define_cpu_unit "ppc8540_siu0_stage0,ppc8540_siu1_stage0" "ppc8540_most")
+
+;; We could describe here MIU subunits for float multiply, float add
+;; etc. But the result automaton would behave the same way as the
+;; described one pipeline below because MIU can start only one insn
+;; per cycle. Actually we could simplify the automaton more not
+;; describing stages 1-3, the result automata would be the same.
+(define_cpu_unit "ppc8540_miu_stage0,ppc8540_miu_stage1" "ppc8540_most")
+(define_cpu_unit "ppc8540_miu_stage2,ppc8540_miu_stage3" "ppc8540_most")
+
+;; The following unit is used to describe non-pipelined division.
+(define_cpu_unit "ppc8540_miu_div" "ppc8540_long")
+
+;; Here we simplified LSU unit description not describing the stages.
+(define_cpu_unit "ppc8540_lsu" "ppc8540_most")
+
+;; The following units are used to make automata deterministic
+(define_cpu_unit "absent_ppc8540_decode_0" "ppc8540_most")
+(define_cpu_unit "absent_ppc8540_issue_0" "ppc8540_most")
+(define_cpu_unit "absent_ppc8540_retire_0" "ppc8540_retire")
+(define_cpu_unit "absent_ppc8540_siu0_stage0" "ppc8540_most")
+
+;; The following sets to make automata deterministic when option ndfa is used.
+(absence_set "absent_ppc8540_decode_0" "ppc8540_decode_0")
+(absence_set "absent_ppc8540_issue_0" "ppc8540_issue_0")
+(absence_set "absent_ppc8540_retire_0" "ppc8540_retire_0")
+(absence_set "absent_ppc8540_siu0_stage0" "ppc8540_siu0_stage0")
+
+;; Some useful abbreviations.
+(define_reservation "ppc8540_decode"
+ "ppc8540_decode_0|ppc8540_decode_1+absent_ppc8540_decode_0")
+(define_reservation "ppc8540_issue"
+ "ppc8540_issue_0|ppc8540_issue_1+absent_ppc8540_issue_0")
+(define_reservation "ppc8540_retire"
+ "ppc8540_retire_0|ppc8540_retire_1+absent_ppc8540_retire_0")
+(define_reservation "ppc8540_siu_stage0"
+ "ppc8540_siu0_stage0|ppc8540_siu1_stage0+absent_ppc8540_siu0_stage0")
+
+;; Simple SIU insns
+(define_insn_reservation "ppc8540_siu" 1
+ (and (eq_attr "type" "integer,cmp,compare,delayed_compare,fast_compare")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_siu_stage0+ppc8540_retire")
+
+;; Branch. Actually this latency time is not used by the scheduler.
+(define_insn_reservation "ppc8540_branch" 1
+ (and (eq_attr "type" "jmpreg,branch")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_bu+ppc8540_retire")
+
+;; Multiply
+(define_insn_reservation "ppc8540_multiply" 4
+ (and (eq_attr "type" "imul,imul2,imul3,mult_compare")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0,ppc8540_miu_stage1,\
+ ppc8540_miu_stage2,ppc8540_miu_stage3,ppc8540_retire")
+
+;; Divide. We use the average latency time here. We omit reserving a
+;; retire unit because of the result automata will be huge.
+(define_insn_reservation "ppc8540_divide" 14
+ (and (eq_attr "type" "idiv")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0+ppc8540_miu_div,\
+ ppc8540_miu_div*13")
+
+;; CR logical
+(define_insn_reservation "ppc8540_cr_logical" 1
+ (and (eq_attr "type" "cr_logical,delayed_cr")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_bu+ppc8540_retire")
+
+;; Mfcr
+(define_insn_reservation "ppc8540_mfcr" 1
+ (and (eq_attr "type" "mfcr")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_siu1_stage0+ppc8540_retire")
+
+;; Mtcrf
+(define_insn_reservation "ppc8540_mtcrf" 1
+ (and (eq_attr "type" "mtcr")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_siu1_stage0+ppc8540_retire")
+
+;; Mtjmpr
+(define_insn_reservation "ppc8540_mtjmpr" 1
+ (and (eq_attr "type" "mtjmpr")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_siu_stage0+ppc8540_retire")
+
+;; Loads
+(define_insn_reservation "ppc8540_load" 3
+ (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing*2,ppc8540_retire")
+
+;; Stores.
+(define_insn_reservation "ppc8540_store" 3
+ (and (eq_attr "type" "store,store_ux,store_u")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing*2,ppc8540_retire")
+
+;; Simple FP
+(define_insn_reservation "ppc8540_simple_float" 1
+ (and (eq_attr "type" "fpsimple")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_siu_stage0,ppc8540_retire")
+
+;; FP
+(define_insn_reservation "ppc8540_float" 4
+ (and (eq_attr "type" "fp")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0,ppc8540_miu_stage1,\
+ ppc8540_miu_stage2,ppc8540_miu_stage3+ppc8540_retire")
+
+;; float divides. We omit reserving a retire unit because of the
+;; result automata will be huge.
+(define_insn_reservation "ppc8540_float_vector_divide" 29
+ (and (eq_attr "type" "vecfdiv")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0+ppc8540_miu_div,\
+ ppc8540_miu_div*28")
+
+;; Brinc
+(define_insn_reservation "ppc8540_brinc" 1
+ (and (eq_attr "type" "brinc")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_siu_stage0+ppc8540_retire")
+
+;; Simple vector
+(define_insn_reservation "ppc8540_simple_vector" 1
+ (and (eq_attr "type" "vecsimple")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_siu1_stage0+ppc8540_retire")
+
+;; Simple vector compare
+(define_insn_reservation "ppc8540_simple_vector_compare" 1
+ (and (eq_attr "type" "veccmpsimple")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_siu_stage0+ppc8540_retire")
+
+;; Vector compare
+(define_insn_reservation "ppc8540_vector_compare" 1
+ (and (eq_attr "type" "veccmp")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_siu1_stage0+ppc8540_retire")
+
+;; evsplatfi evsplati
+(define_insn_reservation "ppc8540_vector_perm" 1
+ (and (eq_attr "type" "vecperm")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_siu1_stage0+ppc8540_retire")
+
+;; Vector float
+(define_insn_reservation "ppc8540_float_vector" 4
+ (and (eq_attr "type" "vecfloat")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0,ppc8540_miu_stage1,\
+ ppc8540_miu_stage2,ppc8540_miu_stage3+ppc8540_retire")
+
+;; Vector divides: Use the average. We omit reserving a retire unit
+;; because of the result automata will be huge.
+(define_insn_reservation "ppc8540_vector_divide" 14
+ (and (eq_attr "type" "vecdiv")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0+ppc8540_miu_div,\
+ ppc8540_miu_div*13")
+
+;; Complex vector.
+(define_insn_reservation "ppc8540_complex_vector" 4
+ (and (eq_attr "type" "veccomplex")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0,ppc8540_miu_stage1,\
+ ppc8540_miu_stage2,ppc8540_miu_stage3+ppc8540_retire")
+
+;; Vector load
+(define_insn_reservation "ppc8540_vector_load" 3
+ (and (eq_attr "type" "vecload")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing*2,ppc8540_retire")
+
+;; Vector store
+(define_insn_reservation "ppc8540_vector_store" 3
+ (and (eq_attr "type" "vecstore")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing*2,ppc8540_retire")
"iu_mpc")
(define_insn_reservation "mpccore-imul" 2
- (and (eq_attr "type" "imul,imul2,imul3")
+ (and (eq_attr "type" "imul,imul2,imul3,mult_compare")
(eq_attr "cpu" "mpccore"))
"mciu_mpc")
(define_bypass 2 "power4-compare" "power4-integer")
(define_insn_reservation "power4-imul" 7
- (and (eq_attr "type" "imul,lmul")
+ (and (eq_attr "type" "imul,lmul,mult_compare")
(eq_attr "cpu" "power4"))
"(q1_power4,iu1_power4*6)|(q2_power4,iu2_power4*6)")
"iu_rios1")
(define_insn_reservation "rios1-imul" 5
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,mult_compare")
(eq_attr "cpu" "rios1"))
"iu_rios1*5")
"iu_rios1*4")
(define_insn_reservation "rios1-imul3" 3
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,mult_compare")
(eq_attr "cpu" "rios1"))
"iu_rios1*3")
(define_insn_reservation "ppc601-imul" 5
- (and (eq_attr "type" "imul,imul2,imul3")
+ (and (eq_attr "type" "imul,imul2,imul3,mult_compare")
(eq_attr "cpu" "ppc601"))
"iu_rios1*5")
"iu1_rios2|iu2_rios2")
(define_insn_reservation "rios2-imul" 2
- (and (eq_attr "type" "imul,imul2,imul3")
+ (and (eq_attr "type" "imul,imul2,imul3,mult_compare")
(eq_attr "cpu" "rios2"))
"iu1_rios2*2")
\f
;; Define an insn type attribute. This is used in function unit delay
;; computations.
-(define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,cmp,fast_compare,compare,delayed_compare,fpcompare,cr_logical,delayed_cr,mfcr,mtcr,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,vecsimple,veccomplex,veccmp,vecperm,vecfloat"
+(define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,cmp,fast_compare,compare,delayed_compare,mult_compare,fpcompare,cr_logical,delayed_cr,mfcr,mtcr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
(const_string "integer"))
;; Length (in bytes).
(include "6xx.md")
(include "7xx.md")
(include "7450.md")
+(include "8540.md")
(include "power4.md")
\f
"@
{muls.|mullw.} %3,%1,%2
#"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "mult_compare")
(set_attr "length" "4,8")])
(define_split
"@
{muls.|mullw.} %3,%1,%2
#"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "mult_compare")
(set_attr "length" "4,8")])
(define_split
"@
{muls.|mullw.} %0,%1,%2
#"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "mult_compare")
(set_attr "length" "4,8")])
(define_split
"@
{muls.|mullw.} %0,%1,%2
#"
- [(set_attr "type" "delayed_compare")
+ [(set_attr "type" "mult_compare")
(set_attr "length" "4,8")])
(define_split
"iu_rs64")
(define_insn_reservation "rs64a-imul" 20
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,mult_compare")
(eq_attr "cpu" "rs64a"))
"mciu_rs64*13")
(neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efsneg %0,%1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "fpsimple")])
(define_insn "*abssf2_gpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efsabs %0,%1"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "fpsimple")])
(define_insn "*addsf3_gpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(match_operand:SF 2 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efsdiv %0,%1,%2"
- [(set_attr "type" "fp")])
+ [(set_attr "type" "vecfdiv")])
(define_insn "spe_efsctuiz"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
"TARGET_SPE"
"evfsabs %0,%1"
- [(set_attr "type" "vecfloat")
+ [(set_attr "type" "vecsimple")
(set_attr "length" "4")])
(define_insn "spe_evfsadd"
(clobber (reg:SI SPEFSCR_REGNO))]
"TARGET_SPE"
"evfsdiv %0,%1,%2"
- [(set_attr "type" "vecfloat")
+ [(set_attr "type" "vecfdiv")
(set_attr "length" "4")])
(define_insn "spe_evfsmul"
(unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 537))]
"TARGET_SPE"
"evfsnabs %0,%1"
- [(set_attr "type" "vecfloat")
+ [(set_attr "type" "vecsimple")
(set_attr "length" "4")])
(define_insn "spe_evfsneg"
(neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
"TARGET_SPE"
"evfsneg %0,%1"
- [(set_attr "type" "vecfloat")
+ [(set_attr "type" "vecsimple")
(set_attr "length" "4")])
(define_insn "spe_evfssub"
(match_operand:SI 2 "gpc_reg_operand" "r")] 556))]
"TARGET_SPE"
"brinc %0,%1,%2"
- [(set_attr "type" "veccomplex")
+ [(set_attr "type" "brinc")
(set_attr "length" "4")])
(define_insn "spe_evmhegsmfaa"
(match_operand:V2SI 2 "gpc_reg_operand" "r")))]
"TARGET_SPE"
"evaddw %0,%1,%2"
- [(set_attr "type" "veccomplex")
+ [(set_attr "type" "vecsimple")
(set_attr "length" "4")])
(define_insn "spe_evaddusiaaw"
(match_operand:QI 2 "immediate_operand" "i")] 677))]
"TARGET_SPE"
"evaddiw %0,%1,%2"
- [(set_attr "type" "veccomplex")
+ [(set_attr "type" "vecsimple")
(set_attr "length" "4")])
(define_insn "spe_evsubifw"
(clobber (reg:SI SPEFSCR_REGNO))]
"TARGET_SPE"
"evdivws %0,%1,%2"
- [(set_attr "type" "veccomplex")
+ [(set_attr "type" "vecdiv")
(set_attr "length" "4")])
(define_insn "spe_evdivwu"
(clobber (reg:SI SPEFSCR_REGNO))]
"TARGET_SPE"
"evdivwu %0,%1,%2"
- [(set_attr "type" "veccomplex")
+ [(set_attr "type" "vecdiv")
(set_attr "length" "4")])
(define_insn "spe_evsplatfi"
evstdd%X0 %1,%y0
evldd%X1 %0,%y1
evor %0,%1,%1"
- [(set_attr "type" "vecload")])
+ [(set_attr "type" "vecload,vecload,vecsimple")])
(define_expand "movv1di"
[(set (match_operand:V1DI 0 "nonimmediate_operand" "")
evstdd%X0 %1,%y0
evldd%X1 %0,%y1
evor %0,%1,%1"
- [(set_attr "type" "vecload")])
+ [(set_attr "type" "vecload,vecload,vecsimple")])
(define_expand "movv4hi"
[(set (match_operand:V4HI 0 "nonimmediate_operand" "")
evstdd%X0 %1,%y0
evldd%X1 %0,%y1
evor %0,%1,%1"
- [(set_attr "type" "vecload")])
+ [(set_attr "type" "vecload,vecload,vecsimple")])
(define_expand "movv2sf"
[(set (match_operand:V2SF 0 "nonimmediate_operand" "")
evstdd%X0 %1,%y0
evldd%X1 %0,%y1
evor %0,%1,%1"
- [(set_attr "type" "vecload")])
+ [(set_attr "type" "vecload,vecload,vecsimple")])
(define_insn "spe_evmwhssfaa"
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
(match_operand:SF 2 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
"efscmpeq %0,%1,%2"
- [(set_attr "type" "fpcompare")])
+ [(set_attr "type" "veccmp")])
(define_insn "tstsfeq_gpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(match_operand:SF 2 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
"efststeq %0,%1,%2"
- [(set_attr "type" "fpcompare")])
+ [(set_attr "type" "veccmpsimple")])
(define_insn "cmpsfgt_gpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(match_operand:SF 2 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
"efscmpgt %0,%1,%2"
- [(set_attr "type" "fpcompare")])
+ [(set_attr "type" "veccmp")])
(define_insn "tstsfgt_gpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(match_operand:SF 2 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
"efststgt %0,%1,%2"
- [(set_attr "type" "fpcompare")])
+ [(set_attr "type" "veccmpsimple")])
(define_insn "cmpsflt_gpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(match_operand:SF 2 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
"efscmplt %0,%1,%2"
- [(set_attr "type" "fpcompare")])
+ [(set_attr "type" "veccmp")])
(define_insn "tstsflt_gpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(match_operand:SF 2 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
"efststlt %0,%1,%2"
- [(set_attr "type" "fpcompare")])
+ [(set_attr "type" "veccmpsimple")])
projects / thirdparty / gcc.git / commitdiff
