]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
ARM: at91: add support in SoC driver for new sam9x7
authorVarshini Rajendran <varshini.rajendran@microchip.com>
Mon, 29 Jul 2024 07:07:11 +0000 (12:37 +0530)
committerClaudiu Beznea <claudiu.beznea@tuxon.dev>
Wed, 7 Aug 2024 16:24:46 +0000 (19:24 +0300)
Add support for SAM9X7 SoC in the SoC driver.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20240729070711.1990605-1-varshini.rajendran@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
drivers/soc/atmel/soc.c
drivers/soc/atmel/soc.h

index cc9a3e107479ab8778628defe04703d759765b8d..2a42b28931c96d1d80fb8163862a2d2ec62771f7 100644 (file)
@@ -101,6 +101,29 @@ static const struct at91_soc socs[] __initconst = {
                 AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH,
                 "sam9x60 8MiB SDRAM SiP", "sam9x60"),
 #endif
+#ifdef CONFIG_SOC_SAM9X7
+       AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+                AT91_CIDR_VERSION_MASK, SAM9X70_EXID_MATCH,
+                "sam9x70", "sam9x7"),
+       AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+                AT91_CIDR_VERSION_MASK, SAM9X72_EXID_MATCH,
+                "sam9x72", "sam9x7"),
+       AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+                AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+                "sam9x75", "sam9x7"),
+       AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1M_EXID_MATCH,
+                AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+                "sam9x75 16MB DDR2 SiP", "sam9x7"),
+       AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D5M_EXID_MATCH,
+                AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+                "sam9x75 64MB DDR2 SiP", "sam9x7"),
+       AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1G_EXID_MATCH,
+                AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+                "sam9x75 125MB DDR3L SiP ", "sam9x7"),
+       AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D2G_EXID_MATCH,
+                AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+                "sam9x75 250MB DDR3L SiP", "sam9x7"),
+#endif
 #ifdef CONFIG_SOC_SAMA5
        AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
                 AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH,
index 7a9f47ce85fb323f3a8be16a5ecc6cc0f35bc14d..2c78e54255f7f818d737250616f0d49bc3f687d6 100644 (file)
@@ -44,6 +44,7 @@ at91_soc_init(const struct at91_soc *socs);
 #define AT91SAM9X5_CIDR_MATCH          0x019a05a0
 #define AT91SAM9N12_CIDR_MATCH         0x019a07a0
 #define SAM9X60_CIDR_MATCH             0x019b35a0
+#define SAM9X7_CIDR_MATCH              0x09750020
 #define SAMA7G5_CIDR_MATCH             0x00162100
 
 #define AT91SAM9M11_EXID_MATCH         0x00000001
@@ -66,6 +67,14 @@ at91_soc_init(const struct at91_soc *socs);
 #define SAM9X60_D1G_EXID_MATCH         0x00000010
 #define SAM9X60_D6K_EXID_MATCH         0x00000011
 
+#define SAM9X70_EXID_MATCH             0x00000005
+#define SAM9X72_EXID_MATCH             0x00000004
+#define SAM9X75_D1G_EXID_MATCH         0x00000018
+#define SAM9X75_D2G_EXID_MATCH         0x00000020
+#define SAM9X75_D1M_EXID_MATCH         0x00000003
+#define SAM9X75_D5M_EXID_MATCH         0x00000010
+#define SAM9X75_EXID_MATCH             0x00000000
+
 #define SAMA7G51_EXID_MATCH            0x3
 #define SAMA7G52_EXID_MATCH            0x2
 #define SAMA7G53_EXID_MATCH            0x1