]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
ARM: dts: qcom: msm8960: Add BAM
authorRudraksha Gupta <guptarud@gmail.com>
Fri, 14 Feb 2025 06:28:39 +0000 (22:28 -0800)
committerBjorn Andersson <andersson@kernel.org>
Thu, 13 Mar 2025 21:39:24 +0000 (16:39 -0500)
Copy bam nodes from qcom-ipq8064.dtsi and change
the reg values to match msm8960.

Co-developed-by: Sam Day <me@samcday.com>
Signed-off-by: Sam Day <me@samcday.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Rudraksha Gupta <guptarud@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250213-expressatt-bam-v3-1-0ff338f488b2@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arch/arm/boot/dts/qcom/qcom-msm8960.dtsi

index 865fe7cc39511d7cb9ec5c4b12100404f77e2989..1a98a4a9a586164451e2777c53d978cf47ce3d24 100644 (file)
                        compatible = "arm,pl18x", "arm,primecell";
                        arm,primecell-periphid = <0x00051180>;
                        status = "disabled";
-                       reg = <0x12180000 0x8000>;
+                       reg = <0x12180000 0x2000>;
                        interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
                        clock-names = "mclk", "apb_pclk";
                        max-frequency = <192000000>;
                        no-1-8-v;
                        vmmc-supply = <&vsdcc_fixed>;
+                       dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
+                       dma-names = "tx", "rx";
+               };
+
+               sdcc3bam: dma-controller@12182000 {
+                       compatible = "qcom,bam-v1.3.0";
+                       reg = <0x12182000 0x4000>;
+                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&gcc SDC3_H_CLK>;
+                       clock-names = "bam_clk";
+                       #dma-cells = <1>;
+                       qcom,ee = <0>;
                };
 
                sdcc1: mmc@12400000 {
                        status = "disabled";
                        compatible = "arm,pl18x", "arm,primecell";
                        arm,primecell-periphid = <0x00051180>;
-                       reg = <0x12400000 0x8000>;
+                       reg = <0x12400000 0x2000>;
                        interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
                        clock-names = "mclk", "apb_pclk";
                        cap-sd-highspeed;
                        cap-mmc-highspeed;
                        vmmc-supply = <&vsdcc_fixed>;
+                       dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
+                       dma-names = "tx", "rx";
+               };
+
+               sdcc1bam: dma-controller@12402000 {
+                       compatible = "qcom,bam-v1.3.0";
+                       reg = <0x12402000 0x4000>;
+                       interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&gcc SDC1_H_CLK>;
+                       clock-names = "bam_clk";
+                       #dma-cells = <1>;
+                       qcom,ee = <0>;
                };
 
                tcsr: syscon@1a400000 {