RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 0

Add asm dump check and for vec_duplicate + vadd.vv combine case 1 to vadd.vx.
The late-combine will take action when GR2VR cost is 0, because the vmv
and the vadd.vx will consume the same cost of GR2VR.  Aka:

Before:
L1:
  vmv.v.x
  vadd.vv
  J L1

After:
L1:
  vadd.vx
  J L1

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test
	helper macros.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
index de5b70dd04b64d82df4e329a581722de955107f9..db802bdefd741766762d7a3b5249eef37fba9014 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
@@ -14,4 +14,48 @@ test_vx_binary_case_0 (T * restrict out, T * restrict in, T x, unsigned n) \
 #define RUN_VX_BINARY_CASE_0(out, in, x, n)      test_vx_binary_case_0(out, in, x, n)
 #define RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) RUN_VX_BINARY_CASE_0(out, in, x, n)
 
+#define VX_BINARY_BODY(op)       \
+  out[k + 0] = in[k + 0] op tmp; \
+  out[k + 1] = in[k + 1] op tmp; \
+  k += 2;
+
+#define VX_BINARY_BODY_X4(op) \
+  VX_BINARY_BODY(op)          \
+  VX_BINARY_BODY(op)
+
+#define VX_BINARY_BODY_X8(op) \
+  VX_BINARY_BODY_X4(op)       \
+  VX_BINARY_BODY_X4(op)
+
+#define VX_BINARY_BODY_X16(op) \
+  VX_BINARY_BODY_X8(op)        \
+  VX_BINARY_BODY_X8(op)
+
+#define VX_BINARY_BODY_X32(op) \
+  VX_BINARY_BODY_X16(op)       \
+  VX_BINARY_BODY_X16(op)
+
+#define VX_BINARY_BODY_X64(op) \
+  VX_BINARY_BODY_X32(op)       \
+  VX_BINARY_BODY_X32(op)
+
+#define VX_BINARY_BODY_X128(op) \
+  VX_BINARY_BODY_X64(op)        \
+  VX_BINARY_BODY_X64(op)
+
+#define DEF_VX_BINARY_CASE_1(T, OP, BODY)                                  \
+void                                                                       \
+test_vx_binary_case_1 (T * restrict out, T * restrict in, T x, unsigned n) \
+{                                                                          \
+  unsigned k = 0;                                                          \
+  T tmp = x + 3;                                                           \
+                                                                           \
+  while (k < n)                                                            \
+    {                                                                      \
+      tmp = tmp ^ 0x3f;                                                    \
+      BODY(OP)                                                             \
+    }                                                                      \
+}
+#define DEF_VX_BINARY_CASE_1_WRAP(T, OP, BODY) DEF_VX_BINARY_CASE_1(T, OP, BODY)
+
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c
new file mode 100644 (file)
index 0000000..9a26601
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int16_t, +, VX_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler {vadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c
new file mode 100644 (file)
index 0000000..55b51fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int32_t, +, VX_BINARY_BODY_X4)
+
+/* { dg-final { scan-assembler {vadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c
new file mode 100644 (file)
index 0000000..8ad6098
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int64_t, +, VX_BINARY_BODY)
+
+/* { dg-final { scan-assembler {vadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c
new file mode 100644 (file)
index 0000000..193e020
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int8_t, +, VX_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler {vadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c
new file mode 100644 (file)
index 0000000..a093fca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(uint16_t, +, VX_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler {vadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c
new file mode 100644 (file)
index 0000000..9f5843b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(uint32_t, +, VX_BINARY_BODY_X4)
+
+/* { dg-final { scan-assembler {vadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c
new file mode 100644 (file)
index 0000000..0f00688
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(uint64_t, +, VX_BINARY_BODY)
+
+/* { dg-final { scan-assembler {vadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c
new file mode 100644 (file)
index 0000000..47707e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(uint8_t, +, VX_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler {vadd.vx} } } */