--- /dev/null
+From dad7b9896a5dbac5da8275d5a6147c65c81fb5f2 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Fri, 14 May 2021 11:26:37 +0100
+Subject: ARM: 9081/1: fix gcc-10 thumb2-kernel regression
+
+From: Arnd Bergmann <arnd@arndb.de>
+
+commit dad7b9896a5dbac5da8275d5a6147c65c81fb5f2 upstream.
+
+When building the kernel wtih gcc-10 or higher using the
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y flag, the compiler picks a slightly
+different set of registers for the inline assembly in cpu_init() that
+subsequently results in a corrupt kernel stack as well as remaining in
+FIQ mode. If a banked register is used for the last argument, the wrong
+version of that register gets loaded into CPSR_c. When building in Arm
+mode, the arguments are passed as immediate values and the bug cannot
+happen.
+
+This got introduced when Daniel reworked the FIQ handling and was
+technically always broken, but happened to work with both clang and gcc
+before gcc-10 as long as they picked one of the lower registers.
+This is probably an indication that still very few people build the
+kernel in Thumb2 mode.
+
+Marek pointed out the problem on IRC, Arnd narrowed it down to this
+inline assembly and Russell pinpointed the exact bug.
+
+Change the constraints to force the final mode switch to use a non-banked
+register for the argument to ensure that the correct constant gets loaded.
+Another alternative would be to always use registers for the constant
+arguments to avoid the #ifdef that has now become more complex.
+
+Cc: <stable@vger.kernel.org> # v3.18+
+Cc: Daniel Thompson <daniel.thompson@linaro.org>
+Reported-by: Marek Vasut <marek.vasut@gmail.com>
+Acked-by: Ard Biesheuvel <ardb@kernel.org>
+Fixes: c0e7f7ee717e ("ARM: 8150/3: fiq: Replace default FIQ handler")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/arm/kernel/setup.c | 16 +++++++++-------
+ 1 file changed, 9 insertions(+), 7 deletions(-)
+
+--- a/arch/arm/kernel/setup.c
++++ b/arch/arm/kernel/setup.c
+@@ -544,9 +544,11 @@ void notrace cpu_init(void)
+ * In Thumb-2, msr with an immediate value is not allowed.
+ */
+ #ifdef CONFIG_THUMB2_KERNEL
+-#define PLC "r"
++#define PLC_l "l"
++#define PLC_r "r"
+ #else
+-#define PLC "I"
++#define PLC_l "I"
++#define PLC_r "I"
+ #endif
+
+ /*
+@@ -568,15 +570,15 @@ void notrace cpu_init(void)
+ "msr cpsr_c, %9"
+ :
+ : "r" (stk),
+- PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
++ PLC_r (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
+ "I" (offsetof(struct stack, irq[0])),
+- PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
++ PLC_r (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
+ "I" (offsetof(struct stack, abt[0])),
+- PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
++ PLC_r (PSR_F_BIT | PSR_I_BIT | UND_MODE),
+ "I" (offsetof(struct stack, und[0])),
+- PLC (PSR_F_BIT | PSR_I_BIT | FIQ_MODE),
++ PLC_r (PSR_F_BIT | PSR_I_BIT | FIQ_MODE),
+ "I" (offsetof(struct stack, fiq[0])),
+- PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
++ PLC_l (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
+ : "r14");
+ #endif
+ }
--- /dev/null
+From 17b11f71795abdce46f62a808f906857e525cea8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Mon, 21 Jun 2021 13:36:35 +0200
+Subject: drm/nouveau: wait for moving fence after pinning v2
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Christian König <christian.koenig@amd.com>
+
+commit 17b11f71795abdce46f62a808f906857e525cea8 upstream.
+
+We actually need to wait for the moving fence after pinning
+the BO to make sure that the pin is completed.
+
+v2: grab the lock while waiting
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+References: https://lore.kernel.org/dri-devel/20210621151758.2347474-1-daniel.vetter@ffwll.ch/
+CC: stable@kernel.org
+Link: https://patchwork.freedesktop.org/patch/msgid/20210622114506.106349-1-christian.koenig@amd.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/nouveau/nouveau_prime.c | 17 ++++++++++++++++-
+ 1 file changed, 16 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/nouveau/nouveau_prime.c
++++ b/drivers/gpu/drm/nouveau/nouveau_prime.c
+@@ -112,7 +112,22 @@ int nouveau_gem_prime_pin(struct drm_gem
+ if (ret)
+ return -EINVAL;
+
+- return 0;
++ ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
++ if (ret)
++ goto error;
++
++ if (nvbo->bo.moving)
++ ret = dma_fence_wait(nvbo->bo.moving, true);
++
++ ttm_bo_unreserve(&nvbo->bo);
++ if (ret)
++ goto error;
++
++ return ret;
++
++error:
++ nouveau_bo_unpin(nvbo);
++ return ret;
+ }
+
+ void nouveau_gem_prime_unpin(struct drm_gem_object *obj)
--- /dev/null
+From 4b41726aae563273bb4b4a9462ba51ce4d372f78 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Mon, 21 Jun 2021 13:43:05 +0200
+Subject: drm/radeon: wait for moving fence after pinning
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Christian König <christian.koenig@amd.com>
+
+commit 4b41726aae563273bb4b4a9462ba51ce4d372f78 upstream.
+
+We actually need to wait for the moving fence after pinning
+the BO to make sure that the pin is completed.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+References: https://lore.kernel.org/dri-devel/20210621151758.2347474-1-daniel.vetter@ffwll.ch/
+CC: stable@kernel.org
+Link: https://patchwork.freedesktop.org/patch/msgid/20210622114506.106349-2-christian.koenig@amd.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/radeon/radeon_prime.c | 14 ++++++++++++--
+ 1 file changed, 12 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_prime.c
++++ b/drivers/gpu/drm/radeon/radeon_prime.c
+@@ -94,9 +94,19 @@ int radeon_gem_prime_pin(struct drm_gem_
+
+ /* pin buffer into GTT */
+ ret = radeon_bo_pin(bo, RADEON_GEM_DOMAIN_GTT, NULL);
+- if (likely(ret == 0))
+- bo->prime_shared_count++;
++ if (unlikely(ret))
++ goto error;
+
++ if (bo->tbo.moving) {
++ ret = dma_fence_wait(bo->tbo.moving, false);
++ if (unlikely(ret)) {
++ radeon_bo_unpin(bo);
++ goto error;
++ }
++ }
++
++ bo->prime_shared_count++;
++error:
+ radeon_bo_unreserve(bo);
+ return ret;
+ }
--- /dev/null
+From 103a5348c22c3fca8b96c735a9e353b8a0801842 Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <narmstrong@baylibre.com>
+Date: Wed, 9 Jun 2021 17:02:30 +0200
+Subject: mmc: meson-gx: use memcpy_to/fromio for dram-access-quirk
+
+From: Neil Armstrong <narmstrong@baylibre.com>
+
+commit 103a5348c22c3fca8b96c735a9e353b8a0801842 upstream.
+
+It has been reported that usage of memcpy() to/from an iomem mapping is invalid,
+and a recent arm64 memcpy update [1] triggers a memory abort when dram-access-quirk
+is used on the G12A/G12B platforms.
+
+This adds a local sg_copy_to_buffer which makes usage of io versions of memcpy
+when dram-access-quirk is enabled.
+
+[1] 285133040e6c ("arm64: Import latest memcpy()/memmove() implementation")
+
+Fixes: acdc8e71d9bb ("mmc: meson-gx: add dram-access-quirk")
+Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
+Suggested-by: Mark Rutland <mark.rutland@arm.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
+Link: https://lore.kernel.org/r/20210609150230.9291-1-narmstrong@baylibre.com
+Cc: stable@vger.kernel.org
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/mmc/host/meson-gx-mmc.c | 50 ++++++++++++++++++++++++++++++++++++----
+ 1 file changed, 45 insertions(+), 5 deletions(-)
+
+--- a/drivers/mmc/host/meson-gx-mmc.c
++++ b/drivers/mmc/host/meson-gx-mmc.c
+@@ -166,6 +166,7 @@ struct meson_host {
+
+ unsigned int bounce_buf_size;
+ void *bounce_buf;
++ void __iomem *bounce_iomem_buf;
+ dma_addr_t bounce_dma_addr;
+ struct sd_emmc_desc *descs;
+ dma_addr_t descs_dma_addr;
+@@ -737,6 +738,47 @@ static void meson_mmc_desc_chain_transfe
+ writel(start, host->regs + SD_EMMC_START);
+ }
+
++/* local sg copy to buffer version with _to/fromio usage for dram_access_quirk */
++static void meson_mmc_copy_buffer(struct meson_host *host, struct mmc_data *data,
++ size_t buflen, bool to_buffer)
++{
++ unsigned int sg_flags = SG_MITER_ATOMIC;
++ struct scatterlist *sgl = data->sg;
++ unsigned int nents = data->sg_len;
++ struct sg_mapping_iter miter;
++ unsigned int offset = 0;
++
++ if (to_buffer)
++ sg_flags |= SG_MITER_FROM_SG;
++ else
++ sg_flags |= SG_MITER_TO_SG;
++
++ sg_miter_start(&miter, sgl, nents, sg_flags);
++
++ while ((offset < buflen) && sg_miter_next(&miter)) {
++ unsigned int len;
++
++ len = min(miter.length, buflen - offset);
++
++ /* When dram_access_quirk, the bounce buffer is a iomem mapping */
++ if (host->dram_access_quirk) {
++ if (to_buffer)
++ memcpy_toio(host->bounce_iomem_buf + offset, miter.addr, len);
++ else
++ memcpy_fromio(miter.addr, host->bounce_iomem_buf + offset, len);
++ } else {
++ if (to_buffer)
++ memcpy(host->bounce_buf + offset, miter.addr, len);
++ else
++ memcpy(miter.addr, host->bounce_buf + offset, len);
++ }
++
++ offset += len;
++ }
++
++ sg_miter_stop(&miter);
++}
++
+ static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd)
+ {
+ struct meson_host *host = mmc_priv(mmc);
+@@ -780,8 +822,7 @@ static void meson_mmc_start_cmd(struct m
+ if (data->flags & MMC_DATA_WRITE) {
+ cmd_cfg |= CMD_CFG_DATA_WR;
+ WARN_ON(xfer_bytes > host->bounce_buf_size);
+- sg_copy_to_buffer(data->sg, data->sg_len,
+- host->bounce_buf, xfer_bytes);
++ meson_mmc_copy_buffer(host, data, xfer_bytes, true);
+ dma_wmb();
+ }
+
+@@ -950,8 +991,7 @@ static irqreturn_t meson_mmc_irq_thread(
+ if (meson_mmc_bounce_buf_read(data)) {
+ xfer_bytes = data->blksz * data->blocks;
+ WARN_ON(xfer_bytes > host->bounce_buf_size);
+- sg_copy_from_buffer(data->sg, data->sg_len,
+- host->bounce_buf, xfer_bytes);
++ meson_mmc_copy_buffer(host, data, xfer_bytes, false);
+ }
+
+ next_cmd = meson_mmc_get_next_command(cmd);
+@@ -1179,7 +1219,7 @@ static int meson_mmc_probe(struct platfo
+ * instead of the DDR memory
+ */
+ host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;
+- host->bounce_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
++ host->bounce_iomem_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
+ host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;
+ } else {
+ /* data bounce buffer */
--- /dev/null
+From baacf52a473b24e10322b67757ddb92ab8d86717 Mon Sep 17 00:00:00 2001
+From: Yifan Zhang <yifan1.zhang@amd.com>
+Date: Sat, 19 Jun 2021 11:39:43 +0800
+Subject: Revert "drm/amdgpu/gfx10: enlarge CP_MEC_DOORBELL_RANGE_UPPER to cover full doorbell."
+
+From: Yifan Zhang <yifan1.zhang@amd.com>
+
+commit baacf52a473b24e10322b67757ddb92ab8d86717 upstream.
+
+This reverts commit 1c0b0efd148d5b24c4932ddb3fa03c8edd6097b3.
+
+Reason for revert: Side effect of enlarging CP_MEC_DOORBELL_RANGE may
+cause some APUs fail to enter gfxoff in certain user cases.
+
+Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +-----
+ 1 file changed, 1 insertion(+), 5 deletions(-)
+
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -3416,12 +3416,8 @@ static int gfx_v10_0_kiq_init_register(s
+ if (ring->use_doorbell) {
+ WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
+ (adev->doorbell_index.kiq * 2) << 2);
+- /* If GC has entered CGPG, ringing doorbell > first page doesn't
+- * wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround
+- * this issue.
+- */
+ WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
+- (adev->doorbell.size - 4));
++ (adev->doorbell_index.userqueue_end * 2) << 2);
+ }
+
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
--- /dev/null
+From ee5468b9f1d3bf48082eed351dace14598e8ca39 Mon Sep 17 00:00:00 2001
+From: Yifan Zhang <yifan1.zhang@amd.com>
+Date: Sat, 19 Jun 2021 11:40:54 +0800
+Subject: Revert "drm/amdgpu/gfx9: fix the doorbell missing when in CGPG issue."
+
+From: Yifan Zhang <yifan1.zhang@amd.com>
+
+commit ee5468b9f1d3bf48082eed351dace14598e8ca39 upstream.
+
+This reverts commit 4cbbe34807938e6e494e535a68d5ff64edac3f20.
+
+Reason for revert: side effect of enlarging CP_MEC_DOORBELL_RANGE may
+cause some APUs fail to enter gfxoff in certain user cases.
+
+Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 +-----
+ 1 file changed, 1 insertion(+), 5 deletions(-)
+
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -3593,12 +3593,8 @@ static int gfx_v9_0_kiq_init_register(st
+ if (ring->use_doorbell) {
+ WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
+ (adev->doorbell_index.kiq * 2) << 2);
+- /* If GC has entered CGPG, ringing doorbell > first page doesn't
+- * wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround
+- * this issue.
+- */
+ WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
+- (adev->doorbell.size - 4));
++ (adev->doorbell_index.userqueue_end * 2) << 2);
+ }
+
+ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
module-limit-enabling-module.sig_enforce.patch
+revert-drm-amdgpu-gfx9-fix-the-doorbell-missing-when-in-cgpg-issue.patch
+revert-drm-amdgpu-gfx10-enlarge-cp_mec_doorbell_range_upper-to-cover-full-doorbell.patch
+drm-nouveau-wait-for-moving-fence-after-pinning-v2.patch
+drm-radeon-wait-for-moving-fence-after-pinning.patch
+arm-9081-1-fix-gcc-10-thumb2-kernel-regression.patch
+mmc-meson-gx-use-memcpy_to-fromio-for-dram-access-quirk.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
