r10k-cache-barrier-10.c: Make a branch-likely instruction more likely.

gcc/testsuite/
	* gcc.target/mips/r10k-cache-barrier-10.c: Make a branch-likely
	instruction more likely.

From-SVN: r194705

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ed50045e74e8487d28153b99df499e455fb34103..315fb0e01cceb451adac7f9e247f13b6b64ffcfd 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2012-12-23  Richard Sandiford  <rdsandiford@googlemail.com>
+
+       * gcc.target/mips/r10k-cache-barrier-10.c: Make a branch-likely
+       instruction more likely.
+
 2012-12-23  Richard Sandiford  <rdsandiford@googlemail.com>
 
        * gcc.target/mips/pr55315.c: Cast to long rather than int.

diff --git a/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c b/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c
index 1b8c6f4ab49c0e9824c8a338d75b0d1521670520..ad0d2b0491bf7306e6b37292a46baffed8ccb0a0 100644 (file)
--- a/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c
+++ b/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c
@@ -9,6 +9,12 @@ unsigned char *bar (int);
 NOMIPS16 void
 foo (unsigned char *n)
 {
+  /* n starts in $4, but will be in $2 after the call to bar.
+     Encourage it to be in $2 on entry to the loop as well,
+     by doing some computation on it beforehand (D?ADDIU $2,$4,4).
+     dbr_schedule should then pull the *n load (L[WD] ...,0($2))
+     into the delay slot.  */
+  n += 4;
   do
     n = bar (*n + 1);
   while (n);