drm/amdgpu: add dynamic workload profile switching for gfx12

Enable dynamic workload profile switching for gfx12.

Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 2523221a2519d3c0f694cdb69639e6160d8b50b0..b5bddebf528e3824afbd2651bd55f4928882010c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -1331,6 +1331,8 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
        int xcc_id = 0;
        struct amdgpu_device *adev = ip_block->adev;
 
+       INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler);
+
        switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
        case IP_VERSION(12, 0, 0):
        case IP_VERSION(12, 0, 1):
@@ -3648,6 +3650,8 @@ static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block)
        struct amdgpu_device *adev = ip_block->adev;
        uint32_t tmp;
 
+       cancel_delayed_work_sync(&adev->gfx.idle_work);
+
        amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
        amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
        amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
@@ -5280,6 +5284,20 @@ static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid)
        return amdgpu_ring_test_ring(ring);
 }
 
+static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring)
+{
+       amdgpu_gfx_profile_ring_begin_use(ring);
+
+       amdgpu_gfx_enforce_isolation_ring_begin_use(ring);
+}
+
+static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring)
+{
+       amdgpu_gfx_profile_ring_end_use(ring);
+
+       amdgpu_gfx_enforce_isolation_ring_end_use(ring);
+}
+
 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = {
        .name = "gfx_v12_0",
        .early_init = gfx_v12_0_early_init,
@@ -5345,8 +5363,8 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = {
        .emit_mem_sync = gfx_v12_0_emit_mem_sync,
        .reset = gfx_v12_0_reset_kgq,
        .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader,
-       .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use,
-       .end_use = amdgpu_gfx_enforce_isolation_ring_end_use,
+       .begin_use = gfx_v12_0_ring_begin_use,
+       .end_use = gfx_v12_0_ring_end_use,
 };
 
 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = {
@@ -5384,8 +5402,8 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = {
        .emit_mem_sync = gfx_v12_0_emit_mem_sync,
        .reset = gfx_v12_0_reset_kcq,
        .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader,
-       .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use,
-       .end_use = amdgpu_gfx_enforce_isolation_ring_end_use,
+       .begin_use = gfx_v12_0_ring_begin_use,
+       .end_use = gfx_v12_0_ring_end_use,
 };
 
 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = {