PCI: qcom-ep: Mask PTM_UPDATING interrupt

When PTM is enabled, PTM_UPDATING interrupt will be fired for each PTM
context update, which will be once every 10ms in the case of auto context
update. Since the interrupt is not strictly needed for making use of PTM,
mask it to avoid the overhead of processing it.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Link: https://patch.msgid.link/20250505-pcie-ptm-v4-4-02d26d51400b@linaro.org

diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 46b1c6d19974a5161c8567ece85750c7b0a270b4..9270429501ae1fbff7ece155af7c735216b61e1d 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -60,6 +60,7 @@
 #define PARF_DEVICE_TYPE                       0x1000
 #define PARF_BDF_TO_SID_CFG                    0x2c00
 #define PARF_INT_ALL_5_MASK                    0x2dcc
+#define PARF_INT_ALL_3_MASK                    0x2e18
 
 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */
 #define PARF_INT_ALL_LINK_DOWN                 BIT(1)
@@ -132,6 +133,9 @@
 /* PARF_INT_ALL_5_MASK fields */
 #define PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR BIT(0)
 
+/* PARF_INT_ALL_3_MASK fields */
+#define PARF_INT_ALL_3_PTM_UPDATING            BIT(4)
+
 /* ELBI registers */
 #define ELBI_SYS_STTS                          0x08
 #define ELBI_CS2_ENABLE                                0xa4
@@ -497,6 +501,10 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
                writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_5_MASK);
        }
 
+       val = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_3_MASK);
+       val &= ~PARF_INT_ALL_3_PTM_UPDATING;
+       writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_3_MASK);
+
        ret = dw_pcie_ep_init_registers(&pcie_ep->pci.ep);
        if (ret) {
                dev_err(dev, "Failed to complete initialization: %d\n", ret);