fbdev-udlfb-add-vm_ops-to-dlfb_ops_mmap-to-prevent-use-after-free.patch
acpi-video-force-native-backlight-on-hp-omen-16-8a44.patch
spi-rockchip-fix-controller-deregistration.patch
+x86-cpu-amd-add-zenx-generations-flags.patch
+x86-cpu-amd-call-the-spectral-chicken-in-the-zen2-init-function.patch
+x86-cpu-amd-rename-init_amd_zn-to-init_amd_zen_common.patch
+x86-cpu-amd-add-x86_feature_zen1.patch
--- /dev/null
+From 8b11c9f96a0ddb679c11e4a8f2d8dae52e9c15af Mon Sep 17 00:00:00 2001
+From: "Borislav Petkov (AMD)" <bp@alien8.de>
+Date: Sat, 2 Dec 2023 12:50:23 +0100
+Subject: x86/CPU/AMD: Add X86_FEATURE_ZEN1
+
+From: "Borislav Petkov (AMD)" <bp@alien8.de>
+
+Commit 232afb557835d6f6859c73bf610bad308c96b131 upstream.
+
+Add a synthetic feature flag specifically for first generation Zen
+machines. There's need to have a generic flag for all Zen generations so
+make X86_FEATURE_ZEN be that flag.
+
+Fixes: 30fa92832f40 ("x86/CPU/AMD: Add ZenX generations flags")
+Suggested-by: Brian Gerst <brgerst@gmail.com>
+Suggested-by: Tom Lendacky <thomas.lendacky@amd.com>
+Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
+Link: https://lore.kernel.org/r/dc3835e3-0731-4230-bbb9-336bbe3d042b@amd.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/x86/include/asm/cpufeatures.h | 3 ++-
+ arch/x86/kernel/cpu/amd.c | 9 +++++----
+ tools/arch/x86/include/asm/cpufeatures.h | 2 +-
+ 3 files changed, 8 insertions(+), 6 deletions(-)
+
+--- a/arch/x86/include/asm/cpufeatures.h
++++ b/arch/x86/include/asm/cpufeatures.h
+@@ -219,7 +219,7 @@
+ #define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */
+ #define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier without a guaranteed RSB flush */
+ #define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */
+-#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU based on Zen microarchitecture */
++#define X86_FEATURE_ZEN ( 7*32+28) /* "" Generic flag for all Zen and newer */
+ #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
+ #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
+ #define X86_FEATURE_MSR_IA32_FEAT_CTL ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
+@@ -309,6 +309,7 @@
+ #define X86_FEATURE_ZEN2 (11*32+28) /* "" CPU based on Zen2 microarchitecture */
+ #define X86_FEATURE_ZEN3 (11*32+29) /* "" CPU based on Zen3 microarchitecture */
+ #define X86_FEATURE_ZEN4 (11*32+30) /* "" CPU based on Zen4 microarchitecture */
++#define X86_FEATURE_ZEN1 (11*32+31) /* "" CPU based on Zen1 microarchitecture */
+
+ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
+ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
+--- a/arch/x86/kernel/cpu/amd.c
++++ b/arch/x86/kernel/cpu/amd.c
+@@ -741,7 +741,7 @@ static void bsp_init_amd(struct cpuinfo_
+ switch (c->x86_model) {
+ case 0x00 ... 0x2f:
+ case 0x50 ... 0x5f:
+- setup_force_cpu_cap(X86_FEATURE_ZEN);
++ setup_force_cpu_cap(X86_FEATURE_ZEN1);
+ break;
+ case 0x30 ... 0x4f:
+ case 0x60 ... 0x7f:
+@@ -1122,12 +1122,13 @@ void init_spectral_chicken(struct cpuinf
+
+ static void init_amd_zen_common(void)
+ {
++ setup_force_cpu_cap(X86_FEATURE_ZEN);
+ #ifdef CONFIG_NUMA
+ node_reclaim_distance = 32;
+ #endif
+ }
+
+-static void init_amd_zen(struct cpuinfo_x86 *c)
++static void init_amd_zen1(struct cpuinfo_x86 *c)
+ {
+ init_amd_zen_common();
+
+@@ -1239,8 +1240,8 @@ static void init_amd(struct cpuinfo_x86
+ case 0x16: init_amd_jg(c); break;
+ }
+
+- if (boot_cpu_has(X86_FEATURE_ZEN))
+- init_amd_zen(c);
++ if (boot_cpu_has(X86_FEATURE_ZEN1))
++ init_amd_zen1(c);
+ else if (boot_cpu_has(X86_FEATURE_ZEN2))
+ init_amd_zen2(c);
+ else if (boot_cpu_has(X86_FEATURE_ZEN3))
+--- a/tools/arch/x86/include/asm/cpufeatures.h
++++ b/tools/arch/x86/include/asm/cpufeatures.h
+@@ -219,7 +219,7 @@
+ #define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */
+ #define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */
+ #define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */
+-#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 or above (Zen) */
++#define X86_FEATURE_ZEN ( 7*32+28) /* "" Generic flag for all Zen and newer */
+ #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
+ #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
+ #define X86_FEATURE_MSR_IA32_FEAT_CTL ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
--- /dev/null
+From 0505eb46841c27ea9767b7b6270862f29deafc02 Mon Sep 17 00:00:00 2001
+From: "Borislav Petkov (AMD)" <bp@alien8.de>
+Date: Tue, 31 Oct 2023 23:30:59 +0100
+Subject: x86/CPU/AMD: Add ZenX generations flags
+
+From: "Borislav Petkov (AMD)" <bp@alien8.de>
+
+Commit 30fa92832f405d5ac9f263e99f62445fa3084008 upstream.
+
+Add X86_FEATURE flags for each Zen generation. They should be used from
+now on instead of checking f/m/s.
+
+Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
+Reviewed-by: Nikolay Borisov <nik.borisov@suse.com>
+Acked-by: Thomas Gleixner <tglx@linutronix.de>
+Link: http://lore.kernel.org/r/20231120104152.13740-2-bp@alien8.de
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/x86/include/asm/cpufeatures.h | 5 ++
+ arch/x86/kernel/cpu/amd.c | 70 +++++++++++++++++++++++++++++++++++--
+ 2 files changed, 72 insertions(+), 3 deletions(-)
+
+--- a/arch/x86/include/asm/cpufeatures.h
++++ b/arch/x86/include/asm/cpufeatures.h
+@@ -219,7 +219,7 @@
+ #define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */
+ #define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier without a guaranteed RSB flush */
+ #define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */
+-#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 or above (Zen) */
++#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU based on Zen microarchitecture */
+ #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
+ #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
+ #define X86_FEATURE_MSR_IA32_FEAT_CTL ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
+@@ -306,6 +306,9 @@
+ #define X86_FEATURE_SRSO_ALIAS (11*32+25) /* "" AMD BTB untrain RETs through aliasing */
+ #define X86_FEATURE_IBPB_ON_VMEXIT (11*32+26) /* "" Issue an IBPB only on VMEXIT */
+ #define X86_FEATURE_APIC_MSRS_FENCE (11*32+27) /* "" IA32_TSC_DEADLINE and X2APIC MSRs need fencing */
++#define X86_FEATURE_ZEN2 (11*32+28) /* "" CPU based on Zen2 microarchitecture */
++#define X86_FEATURE_ZEN3 (11*32+29) /* "" CPU based on Zen3 microarchitecture */
++#define X86_FEATURE_ZEN4 (11*32+30) /* "" CPU based on Zen4 microarchitecture */
+
+ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
+ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
+--- a/arch/x86/kernel/cpu/amd.c
++++ b/arch/x86/kernel/cpu/amd.c
+@@ -735,7 +735,50 @@ static void bsp_init_amd(struct cpuinfo_
+
+ resctrl_cpu_detect(c);
+
++ /* Figure out Zen generations: */
++ switch (c->x86) {
++ case 0x17: {
++ switch (c->x86_model) {
++ case 0x00 ... 0x2f:
++ case 0x50 ... 0x5f:
++ setup_force_cpu_cap(X86_FEATURE_ZEN);
++ break;
++ case 0x30 ... 0x4f:
++ case 0x60 ... 0x7f:
++ case 0x90 ... 0x91:
++ case 0xa0 ... 0xaf:
++ setup_force_cpu_cap(X86_FEATURE_ZEN2);
++ break;
++ default:
++ goto warn;
++ }
++ break;
++ }
++ case 0x19: {
++ switch (c->x86_model) {
++ case 0x00 ... 0x0f:
++ case 0x20 ... 0x5f:
++ setup_force_cpu_cap(X86_FEATURE_ZEN3);
++ break;
++ case 0x10 ... 0x1f:
++ case 0x60 ... 0xaf:
++ setup_force_cpu_cap(X86_FEATURE_ZEN4);
++ break;
++ default:
++ goto warn;
++ }
++ break;
++ }
++ default:
++ break;
++ }
++
+ tsa_init(c);
++
++ return;
++
++warn:
++ WARN_ONCE(1, "Family 0x%x, model: 0x%x??\n", c->x86, c->x86_model);
+ }
+
+ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
+@@ -1081,8 +1124,6 @@ void init_spectral_chicken(struct cpuinf
+
+ static void init_amd_zn(struct cpuinfo_x86 *c)
+ {
+- set_cpu_cap(c, X86_FEATURE_ZEN);
+-
+ #ifdef CONFIG_NUMA
+ node_reclaim_distance = 32;
+ #endif
+@@ -1148,6 +1189,22 @@ static void zenbleed_check(struct cpuinf
+ }
+ }
+
++static void init_amd_zen(struct cpuinfo_x86 *c)
++{
++}
++
++static void init_amd_zen2(struct cpuinfo_x86 *c)
++{
++}
++
++static void init_amd_zen3(struct cpuinfo_x86 *c)
++{
++}
++
++static void init_amd_zen4(struct cpuinfo_x86 *c)
++{
++}
++
+ static void init_amd(struct cpuinfo_x86 *c)
+ {
+ early_init_amd(c);
+@@ -1182,6 +1239,15 @@ static void init_amd(struct cpuinfo_x86
+ case 0x19: init_amd_zn(c); break;
+ }
+
++ if (boot_cpu_has(X86_FEATURE_ZEN))
++ init_amd_zen(c);
++ else if (boot_cpu_has(X86_FEATURE_ZEN2))
++ init_amd_zen2(c);
++ else if (boot_cpu_has(X86_FEATURE_ZEN3))
++ init_amd_zen3(c);
++ else if (boot_cpu_has(X86_FEATURE_ZEN4))
++ init_amd_zen4(c);
++
+ /*
+ * Enable workaround for FXSAVE leak on CPUs
+ * without a XSaveErPtr feature
--- /dev/null
+From 6ea9e49236f62c01f32ea0b3e5c4ce41d1ec0389 Mon Sep 17 00:00:00 2001
+From: "Borislav Petkov (AMD)" <bp@alien8.de>
+Date: Wed, 1 Nov 2023 11:20:01 +0100
+Subject: x86/CPU/AMD: Call the spectral chicken in the Zen2 init function
+
+From: "Borislav Petkov (AMD)" <bp@alien8.de>
+
+Commit cfbf4f992bfce1fa9f2f347a79cbbea0368e7971 upstream.
+
+No functional change.
+
+Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
+Reviewed-by: Nikolay Borisov <nik.borisov@suse.com>
+Link: http://lore.kernel.org/r/20231120104152.13740-6-bp@alien8.de
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/x86/kernel/cpu/amd.c | 7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+--- a/arch/x86/kernel/cpu/amd.c
++++ b/arch/x86/kernel/cpu/amd.c
+@@ -1101,10 +1101,8 @@ void init_spectral_chicken(struct cpuinf
+ *
+ * This suppresses speculation from the middle of a basic block, i.e. it
+ * suppresses non-branch predictions.
+- *
+- * We use STIBP as a heuristic to filter out Zen2 from the rest of F17H
+ */
+- if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && cpu_has(c, X86_FEATURE_AMD_STIBP)) {
++ if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
+ if (!rdmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) {
+ value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT;
+ wrmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value);
+@@ -1195,6 +1193,7 @@ static void init_amd_zen(struct cpuinfo_
+
+ static void init_amd_zen2(struct cpuinfo_x86 *c)
+ {
++ init_spectral_chicken(c);
+ }
+
+ static void init_amd_zen3(struct cpuinfo_x86 *c)
+@@ -1234,7 +1233,7 @@ static void init_amd(struct cpuinfo_x86
+ case 0x12: init_amd_ln(c); break;
+ case 0x15: init_amd_bd(c); break;
+ case 0x16: init_amd_jg(c); break;
+- case 0x17: init_spectral_chicken(c);
++ case 0x17:
+ fallthrough;
+ case 0x19: init_amd_zn(c); break;
+ }
--- /dev/null
+From 714aa4501bd485a70c063fc9e98a44dc9ae277a4 Mon Sep 17 00:00:00 2001
+From: "Borislav Petkov (AMD)" <bp@alien8.de>
+Date: Wed, 1 Nov 2023 12:34:29 +0100
+Subject: x86/CPU/AMD: Rename init_amd_zn() to init_amd_zen_common()
+
+From: "Borislav Petkov (AMD)" <bp@alien8.de>
+
+Commit 7c81ad8e8bc28a1847e87c5afe1bae6bffb2f73e upstream.
+
+Call it from all Zen init functions.
+
+Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
+Reviewed-by: Nikolay Borisov <nik.borisov@suse.com>
+Link: http://lore.kernel.org/r/20231120104152.13740-7-bp@alien8.de
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/x86/kernel/cpu/amd.c | 17 +++++++++--------
+ 1 file changed, 9 insertions(+), 8 deletions(-)
+
+--- a/arch/x86/kernel/cpu/amd.c
++++ b/arch/x86/kernel/cpu/amd.c
+@@ -1120,11 +1120,16 @@ void init_spectral_chicken(struct cpuinf
+ clear_cpu_cap(c, X86_FEATURE_XSAVES);
+ }
+
+-static void init_amd_zn(struct cpuinfo_x86 *c)
++static void init_amd_zen_common(void)
+ {
+ #ifdef CONFIG_NUMA
+ node_reclaim_distance = 32;
+ #endif
++}
++
++static void init_amd_zen(struct cpuinfo_x86 *c)
++{
++ init_amd_zen_common();
+
+ /* Fix up CPUID bits, but only if not virtualised. */
+ if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
+@@ -1187,21 +1192,20 @@ static void zenbleed_check(struct cpuinf
+ }
+ }
+
+-static void init_amd_zen(struct cpuinfo_x86 *c)
+-{
+-}
+-
+ static void init_amd_zen2(struct cpuinfo_x86 *c)
+ {
++ init_amd_zen_common();
+ init_spectral_chicken(c);
+ }
+
+ static void init_amd_zen3(struct cpuinfo_x86 *c)
+ {
++ init_amd_zen_common();
+ }
+
+ static void init_amd_zen4(struct cpuinfo_x86 *c)
+ {
++ init_amd_zen_common();
+ }
+
+ static void init_amd(struct cpuinfo_x86 *c)
+@@ -1233,9 +1237,6 @@ static void init_amd(struct cpuinfo_x86
+ case 0x12: init_amd_ln(c); break;
+ case 0x15: init_amd_bd(c); break;
+ case 0x16: init_amd_jg(c); break;
+- case 0x17:
+- fallthrough;
+- case 0x19: init_amd_zn(c); break;
+ }
+
+ if (boot_cpu_has(X86_FEATURE_ZEN))
projects / thirdparty / kernel / stable-queue.git / commitdiff
