i386: Emulate MMX umulv1siv1di3 with SSE2

Emulate MMX umulv1siv1di3 with SSE2.  Only SSE register source operand
is allowed.

	PR target/89021
	* config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation
	support.
	(*sse2_umulv1siv1di3): Add SSE2 emulation.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@271239 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 01cdde4faf2c9daa2f19d94d7e100d5331e6b70c..2170b2f218840c1fb6137bba3e7c327658bec73f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2019-05-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/89021
+       * config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation
+       support.
+       (*sse2_umulv1siv1di3): Add SSE2 emulation.
+
 2019-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR target/89021

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 6cc9547d2668a904f834b5aacfe84a4ee38d0128..6504ebb17ef15ede367f83eb5078308f4b776231 100644 (file)
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -930,30 +930,36 @@
         (mult:V1DI
          (zero_extend:V1DI
            (vec_select:V1SI
-             (match_operand:V2SI 1 "nonimmediate_operand")
+             (match_operand:V2SI 1 "register_mmxmem_operand")
              (parallel [(const_int 0)])))
          (zero_extend:V1DI
            (vec_select:V1SI
-             (match_operand:V2SI 2 "nonimmediate_operand")
+             (match_operand:V2SI 2 "register_mmxmem_operand")
              (parallel [(const_int 0)])))))]
-  "TARGET_SSE2"
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE2"
   "ix86_fixup_binary_operands_no_copy (MULT, V2SImode, operands);")
 
 (define_insn "*sse2_umulv1siv1di3"
-  [(set (match_operand:V1DI 0 "register_operand" "=y")
+  [(set (match_operand:V1DI 0 "register_operand" "=y,x,Yv")
         (mult:V1DI
          (zero_extend:V1DI
            (vec_select:V1SI
-             (match_operand:V2SI 1 "nonimmediate_operand" "%0")
+             (match_operand:V2SI 1 "register_mmxmem_operand" "%0,0,Yv")
              (parallel [(const_int 0)])))
          (zero_extend:V1DI
            (vec_select:V1SI
-             (match_operand:V2SI 2 "nonimmediate_operand" "ym")
+             (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv")
              (parallel [(const_int 0)])))))]
-  "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V2SImode, operands)"
-  "pmuludq\t{%2, %0|%0, %2}"
-  [(set_attr "type" "mmxmul")
-   (set_attr "mode" "DI")])
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE)
+   && TARGET_SSE2
+   && ix86_binary_operator_ok (MULT, V2SImode, operands)"
+  "@
+   pmuludq\t{%2, %0|%0, %2}
+   pmuludq\t{%2, %0|%0, %2}
+   vpmuludq\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "mmxmul,ssemul,ssemul")
+   (set_attr "mode" "DI,TI,TI")])
 
 (define_expand "mmx_<code>v4hi3"
   [(set (match_operand:V4HI 0 "register_operand")