drm/i915: Bump RING_FAULT engine ID bits

The fault engine ID field has been 5 bits since icl. Bump our
define to match. The extra bits were unused before icl so we
should be able to use the larger mask unconditionally.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-2-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index a6e50af44b4652bf6fa487f719d72f27daaecc46..424b7ff9dbf27bccea704ca906385ea9d8c02f48 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1044,7 +1044,7 @@
 #define GEN12_RING_FAULT_REG                   _MMIO(0xcec4)
 #define XEHP_RING_FAULT_REG                    MCR_REG(0xcec4)
 #define XELPMP_RING_FAULT_REG                  _MMIO(0xcec4)
-#define   GEN8_RING_FAULT_ENGINE_ID(x)         (((x) >> 12) & 0x7)
+#define   GEN8_RING_FAULT_ENGINE_ID(x)         (((x) >> 12) & 0x1f)
 #define   RING_FAULT_GTTSEL_MASK               (1 << 11)
 #define   RING_FAULT_SRCID(x)                  (((x) >> 3) & 0xff)
 #define   RING_FAULT_FAULT_TYPE(x)             (((x) >> 1) & 0x3)