RISC-V: KVM: Fix APLIC in_clrip and clripnum write emulation

In the section "4.7 Precise effects on interrupt-pending bits"
of the RISC-V AIA specification defines that:

"If the source mode is Level1 or Level0 and the interrupt domain
is configured in MSI delivery mode (domaincfg.DM = 1):
The pending bit is cleared whenever the rectified input value is
low, when the interrupt is forwarded by MSI, or by a relevant
write to an in_clrip register or to clripnum."

Update the aplic_write_pending() to match the spec.

Fixes: d8dd9f113e16 ("RISC-V: KVM: Fix APLIC setipnum_le/be write emulation")
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Vincent Chen <vincent.chen@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20241029085542.30541-1-yongxuan.wang@sifive.com
Signed-off-by: Anup Patel <anup@brainfault.org>

diff --git a/arch/riscv/kvm/aia_aplic.c b/arch/riscv/kvm/aia_aplic.c
index da6ff1bade0df5280db8735745017d9bd085963d..f59d1c0c8c43a70a20a1250d641b3758e632878d 100644 (file)
--- a/arch/riscv/kvm/aia_aplic.c
+++ b/arch/riscv/kvm/aia_aplic.c
@@ -143,7 +143,7 @@ static void aplic_write_pending(struct aplic *aplic, u32 irq, bool pending)
        if (sm == APLIC_SOURCECFG_SM_LEVEL_HIGH ||
            sm == APLIC_SOURCECFG_SM_LEVEL_LOW) {
                if (!pending)
-                       goto skip_write_pending;
+                       goto noskip_write_pending;
                if ((irqd->state & APLIC_IRQ_STATE_INPUT) &&
                    sm == APLIC_SOURCECFG_SM_LEVEL_LOW)
                        goto skip_write_pending;
@@ -152,6 +152,7 @@ static void aplic_write_pending(struct aplic *aplic, u32 irq, bool pending)
                        goto skip_write_pending;
        }
 
+noskip_write_pending:
        if (pending)
                irqd->state |= APLIC_IRQ_STATE_PENDING;
        else