riscv: dts: andes: add QiLai SoC device tree

Introduce the initial device tree support for the Andes QiLai SoC.

For further information, you can refer to [1].

[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-7-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/andes/qilai.dtsi
new file mode 100644 (file)
index 0000000..de3de32
--- /dev/null
+++ b/arch/riscv/boot/dts/andes/qilai.dtsi
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Andes Technology Corporation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               timebase-frequency = <62500000>;
+
+               cpu0: cpu@0 {
+                       compatible = "andestech,ax45mp", "riscv";
+                       device_type = "cpu";
+                       reg = <0>;
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm", "xandespmu";
+                       mmu-type = "riscv,sv39";
+                       clock-frequency = <100000000>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <256>;
+                       i-cache-line-size = <64>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <128>;
+                       d-cache-line-size = <64>;
+                       next-level-cache = <&l2_cache>;
+
+                       cpu0_intc: interrupt-controller {
+                               compatible = "andestech,cpu-intc", "riscv,cpu-intc";
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                       };
+               };
+
+               cpu1: cpu@1 {
+                       compatible = "andestech,ax45mp", "riscv";
+                       device_type = "cpu";
+                       reg = <1>;
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm", "xandespmu";
+                       mmu-type = "riscv,sv39";
+                       clock-frequency = <100000000>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <256>;
+                       i-cache-line-size = <64>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <128>;
+                       d-cache-line-size = <64>;
+                       next-level-cache = <&l2_cache>;
+
+                       cpu1_intc: interrupt-controller {
+                               compatible = "andestech,cpu-intc",
+                                            "riscv,cpu-intc";
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                       };
+               };
+
+               cpu2: cpu@2 {
+                       compatible = "andestech,ax45mp", "riscv";
+                       device_type = "cpu";
+                       reg = <2>;
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm", "xandespmu";
+                       mmu-type = "riscv,sv39";
+                       clock-frequency = <100000000>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <256>;
+                       i-cache-line-size = <64>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <128>;
+                       d-cache-line-size = <64>;
+                       next-level-cache = <&l2_cache>;
+
+                       cpu2_intc: interrupt-controller {
+                               compatible = "andestech,cpu-intc",
+                                            "riscv,cpu-intc";
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                       };
+               };
+
+               cpu3: cpu@3 {
+                       compatible = "andestech,ax45mp", "riscv";
+                       device_type = "cpu";
+                       reg = <3>;
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm", "xandespmu";
+                       mmu-type = "riscv,sv39";
+                       clock-frequency = <100000000>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <256>;
+                       i-cache-line-size = <64>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <128>;
+                       d-cache-line-size = <64>;
+                       next-level-cache = <&l2_cache>;
+
+                       cpu3_intc: interrupt-controller {
+                               compatible = "andestech,cpu-intc",
+                                            "riscv,cpu-intc";
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                       };
+               };
+       };
+
+       soc {
+               compatible = "simple-bus";
+               ranges;
+               interrupt-parent = <&plic>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+
+               plmt: timer@100000 {
+                       compatible = "andestech,qilai-plmt", "andestech,plmt0";
+                       reg = <0x0 0x00100000 0x0 0x100000>;
+                       interrupts-extended = <&cpu0_intc 7>,
+                                             <&cpu1_intc 7>,
+                                             <&cpu2_intc 7>,
+                                             <&cpu3_intc 7>;
+               };
+
+               l2_cache: cache-controller@200000 {
+                       compatible = "andestech,qilai-ax45mp-cache",
+                                    "andestech,ax45mp-cache", "cache";
+                       reg = <0x0 0x00200000 0x0 0x100000>;
+                       interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+                       cache-line-size = <64>;
+                       cache-level = <2>;
+                       cache-sets = <2048>;
+                       cache-size = <0x200000>;
+                       cache-unified;
+               };
+
+               plic_sw: interrupt-controller@400000 {
+                       compatible = "andestech,qilai-plicsw",
+                                    "andestech,plicsw";
+                       reg = <0x0 0x00400000 0x0 0x400000>;
+                       interrupts-extended = <&cpu0_intc 3>,
+                                             <&cpu1_intc 3>,
+                                             <&cpu2_intc 3>,
+                                             <&cpu3_intc 3>;
+               };
+
+               plic: interrupt-controller@2000000 {
+                       compatible = "andestech,qilai-plic",
+                                    "andestech,nceplic100";
+                       reg = <0x0 0x02000000 0x0 0x2000000>;
+                       #address-cells = <0>;
+                       #interrupt-cells = <2>;
+                       interrupt-controller;
+                       interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+                                             <&cpu1_intc 11>, <&cpu1_intc 9>,
+                                             <&cpu2_intc 11>, <&cpu2_intc 9>,
+                                             <&cpu3_intc 11>, <&cpu3_intc 9>;
+                       riscv,ndev = <71>;
+               };
+
+               uart0: serial@30300000 {
+                       compatible = "andestech,uart16550", "ns16550a";
+                       reg = <0x0 0x30300000 0x0 0x100000>;
+                       interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-frequency = <50000000>;
+                       reg-offset = <32>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       no-loopback-test;
+               };
+       };
+};