--- /dev/null
+From 1202f794cdaa4f0ba6a456bc034f2db6cfcf5579 Mon Sep 17 00:00:00 2001
+From: Hamza Mahfooz <hamza.mahfooz@amd.com>
+Date: Thu, 21 Mar 2024 16:09:21 -0400
+Subject: drm/amd/display: fix IPX enablement
+
+From: Hamza Mahfooz <hamza.mahfooz@amd.com>
+
+commit 1202f794cdaa4f0ba6a456bc034f2db6cfcf5579 upstream.
+
+We need to re-enable idle power optimizations after entering PSR. Since,
+we get kicked out of idle power optimizations before entering PSR
+(entering PSR requires us to write to DCN registers, which isn't allowed
+while we are in IPS).
+
+Fixes: a9b1a4f684b3 ("drm/amd/display: Add more checks for exiting idle in DC")
+Tested-by: Mark Broadworth <mark.broadworth@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 8 +++++---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h | 2 +-
+ 2 files changed, 6 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+@@ -141,9 +141,8 @@ bool amdgpu_dm_link_setup_psr(struct dc_
+ * amdgpu_dm_psr_enable() - enable psr f/w
+ * @stream: stream state
+ *
+- * Return: true if success
+ */
+-bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
++void amdgpu_dm_psr_enable(struct dc_stream_state *stream)
+ {
+ struct dc_link *link = stream->link;
+ unsigned int vsync_rate_hz = 0;
+@@ -190,7 +189,10 @@ bool amdgpu_dm_psr_enable(struct dc_stre
+ if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1)
+ power_opt |= psr_power_opt_z10_static_screen;
+
+- return dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt);
++ dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt);
++
++ if (link->ctx->dc->caps.ips_support)
++ dc_allow_idle_optimizations(link->ctx->dc, true);
+ }
+
+ /*
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
+@@ -32,7 +32,7 @@
+ #define AMDGPU_DM_PSR_ENTRY_DELAY 5
+
+ void amdgpu_dm_set_psr_caps(struct dc_link *link);
+-bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
++void amdgpu_dm_psr_enable(struct dc_stream_state *stream);
+ bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
+ bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
+ bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);