Improve modes_tieable by returning true in more cases...

Improve modes_tieable by returning true in more cases: allow scalar access
within vectors without requiring an extra move.  Removing these moves helps
the register allocator in deciding whether to use integer or FP registers on
operations that can be done on both.  This saves about 100 instructions in the
gcc.target/aarch64 tests.

A typical example:

	orr     v1.8b, v0.8b, v1.8b
	fmov    x0, d0
	fmov    x1, d1
	add     x0, x1, x0
	ins     v0.d[0], x0
	orr     v0.8b, v1.8b, v0.8b

after:

	orr     v1.8b, v0.8b, v1.8b
	add     d0, d1, d0
	orr     v0.8b, v1.8b, v0.8b

    gcc/
	* config/aarch64/aarch64.c (aarch64_modes_tieable_p):
	Allow scalar/single vector modes to be tieable.

From-SVN: r237597

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index dadbf4e27bd06e5bfeef9af9cbe736e922181ff9..505b5b0e0f307f8e7fd44932a3517e42277aac1d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2016-06-20  Wilco Dijkstra  <wdijkstr@arm.com>
+
+       * config/aarch64/aarch64.c (aarch64_modes_tieable_p):
+       Allow scalar/single vector modes to be tieable.
+
 2016-06-20  Wilco Dijkstra  <wdijkstr@arm.com>
 
        * config/arm/cortex-a57.md (cortex_a57_fp_cpys): Add fcsel.

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 4497002707e8112ff595d739fbeb4ef8481a91e7..46c917a17bc4191b3072a776350c736c0ad5a3df 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -12819,7 +12819,14 @@ aarch64_reverse_mask (enum machine_mode mode)
   return force_reg (V16QImode, mask);
 }
 
-/* Implement MODES_TIEABLE_P.  */
+/* Implement MODES_TIEABLE_P.  In principle we should always return true.
+   However due to issues with register allocation it is preferable to avoid
+   tieing integer scalar and FP scalar modes.  Executing integer operations
+   in general registers is better than treating them as scalar vector
+   operations.  This reduces latency and avoids redundant int<->FP moves.
+   So tie modes if they are either the same class, or vector modes with
+   other vector modes, vector structs or any scalar mode.
+*/
 
 bool
 aarch64_modes_tieable_p (machine_mode mode1, machine_mode mode2)
@@ -12830,9 +12837,12 @@ aarch64_modes_tieable_p (machine_mode mode1, machine_mode mode2)
   /* We specifically want to allow elements of "structure" modes to
      be tieable to the structure.  This more general condition allows
      other rarer situations too.  */
-  if (TARGET_SIMD
-      && aarch64_vector_mode_p (mode1)
-      && aarch64_vector_mode_p (mode2))
+  if (aarch64_vector_mode_p (mode1) && aarch64_vector_mode_p (mode2))
+    return true;
+
+  /* Also allow any scalar modes with vectors.  */
+  if (aarch64_vector_mode_supported_p (mode1)
+      || aarch64_vector_mode_supported_p (mode2))
     return true;
 
   return false;