arm64: dts: renesas: rzg2: Add boot phase tags

bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to describe various node usage during
boot phases with DT.  Add bootph-all for all nodes that are used in the
bootloader on Renesas RZ/G2 SoCs.

All SoC require CPG clock and its input clock, RST Reset, PFC pin
control and PRR ID register access during all stages of the boot
process, those are marked using bootph-all property, and so is the SoC
bus node which contains these IP.

Each board console UART is also marked as bootph-all to make it
available in all stages of the boot process.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250209180616.160253-3-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
index 43f88c199b7880c8f3936f6b59ab0b3a8df477e1..1489bc8d2f4e6416a9097d1f9586ff42c12e800a 100644 (file)
--- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
@@ -282,6 +282,7 @@
 &scif2 {
        pinctrl-0 = <&scif2_pins>;
        pinctrl-names = "default";
+       bootph-all;
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
index 659ae1fed2faa1a4b3578bb30e35c5dbbaedf0aa..4e78139d52f6c853c60e3da103f6b76a46bb3247 100644 (file)
--- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
@@ -289,6 +289,7 @@
 &scif2 {
        pinctrl-0 = <&scif2_pins>;
        pinctrl-names = "default";
+       bootph-all;
 
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index f065ee90649a4a5e45e80fa8463faec5654479ed..c8b87aed92a368b17c31f73d8caaea2479c6aae6 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -215,6 +215,7 @@
                #clock-cells = <0>;
                /* This value must be overridden by the board */
                clock-frequency = <0>;
+               bootph-all;
        };
 
        extalr_clk: extalr {
@@ -222,6 +223,7 @@
                #clock-cells = <0>;
                /* This value must be overridden by the board */
                clock-frequency = <0>;
+               bootph-all;
        };
 
        /* External PCIe clock - can be overridden by the board */
@@ -262,6 +264,8 @@
        soc {
                compatible = "simple-bus";
                interrupt-parent = <&gic>;
+               bootph-all;
+
                #address-cells = <2>;
                #size-cells = <2>;
                ranges;
@@ -400,6 +404,7 @@
                pfc: pinctrl@e6060000 {
                        compatible = "renesas,pfc-r8a774a1";
                        reg = <0 0xe6060000 0 0x50c>;
+                       bootph-all;
                };
 
                cmt0: timer@e60f0000 {
@@ -480,11 +485,13 @@
                        #clock-cells = <2>;
                        #power-domain-cells = <0>;
                        #reset-cells = <1>;
+                       bootph-all;
                };
 
                rst: reset-controller@e6160000 {
                        compatible = "renesas,r8a774a1-rst";
                        reg = <0 0xe6160000 0 0x018c>;
+                       bootph-all;
                };
 
                sysc: system-controller@e6180000 {
@@ -2785,6 +2792,7 @@
                prr: chipid@fff00044 {
                        compatible = "renesas,prr";
                        reg = <0 0xfff00044 0 4>;
+                       bootph-all;
                };
        };
 

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 117cb6950f91f9341df0cb1994722d1ad9810944..f2fc2a2035a1d491f23270ca8d49517f5720c95f 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -108,6 +108,7 @@
                #clock-cells = <0>;
                /* This value must be overridden by the board */
                clock-frequency = <0>;
+               bootph-all;
        };
 
        extalr_clk: extalr {
@@ -115,6 +116,7 @@
                #clock-cells = <0>;
                /* This value must be overridden by the board */
                clock-frequency = <0>;
+               bootph-all;
        };
 
        /* External PCIe clock - can be overridden by the board */
@@ -146,6 +148,8 @@
        soc {
                compatible = "simple-bus";
                interrupt-parent = <&gic>;
+               bootph-all;
+
                #address-cells = <2>;
                #size-cells = <2>;
                ranges;
@@ -284,6 +288,7 @@
                pfc: pinctrl@e6060000 {
                        compatible = "renesas,pfc-r8a774b1";
                        reg = <0 0xe6060000 0 0x50c>;
+                       bootph-all;
                };
 
                cmt0: timer@e60f0000 {
@@ -364,11 +369,13 @@
                        #clock-cells = <2>;
                        #power-domain-cells = <0>;
                        #reset-cells = <1>;
+                       bootph-all;
                };
 
                rst: reset-controller@e6160000 {
                        compatible = "renesas,r8a774b1-rst";
                        reg = <0 0xe6160000 0 0x0200>;
+                       bootph-all;
                };
 
                sysc: system-controller@e6180000 {
@@ -2661,6 +2668,7 @@
                prr: chipid@fff00044 {
                        compatible = "renesas,prr";
                        reg = <0 0xfff00044 0 4>;
+                       bootph-all;
                };
        };
 

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
index b78dbd807d155730fe0f41b05850060f83016fbd..57a281fc49775d9e8ae8f7ad413b314a94f86786 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
@@ -378,6 +378,7 @@
 &scif2 {
        pinctrl-0 = <&scif2_pins>;
        pinctrl-names = "default";
+       bootph-all;
 
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 522e20924e94a24e55f02d04d1ef8171360b0e9e..530ffd29cf13da00c54849e2b030f320a1b4dcbb 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -107,6 +107,7 @@
                #clock-cells = <0>;
                /* This value must be overridden by the board */
                clock-frequency = <0>;
+               bootph-all;
        };
 
        /* External PCIe clock - can be overridden by the board */
@@ -138,6 +139,8 @@
        soc: soc {
                compatible = "simple-bus";
                interrupt-parent = <&gic>;
+               bootph-all;
+
                #address-cells = <2>;
                #size-cells = <2>;
                ranges;
@@ -261,6 +264,7 @@
                pfc: pinctrl@e6060000 {
                        compatible = "renesas,pfc-r8a774c0";
                        reg = <0 0xe6060000 0 0x508>;
+                       bootph-all;
                };
 
                cmt0: timer@e60f0000 {
@@ -341,11 +345,13 @@
                        #clock-cells = <2>;
                        #power-domain-cells = <0>;
                        #reset-cells = <1>;
+                       bootph-all;
                };
 
                rst: reset-controller@e6160000 {
                        compatible = "renesas,r8a774c0-rst";
                        reg = <0 0xe6160000 0 0x0200>;
+                       bootph-all;
                };
 
                sysc: system-controller@e6180000 {
@@ -1957,6 +1963,7 @@
                prr: chipid@fff00044 {
                        compatible = "renesas,prr";
                        reg = <0 0xfff00044 0 4>;
+                       bootph-all;
                };
        };
 

diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index f845ca604de0696ef8667e52b125f278a7c60085..e4dbda8c34d9eaef387e68f21aef565d7810ef73 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -277,6 +277,7 @@
                #clock-cells = <0>;
                /* This value must be overridden by the board */
                clock-frequency = <0>;
+               bootph-all;
        };
 
        extalr_clk: extalr {
@@ -284,6 +285,7 @@
                #clock-cells = <0>;
                /* This value must be overridden by the board */
                clock-frequency = <0>;
+               bootph-all;
        };
 
        /* External PCIe clock - can be overridden by the board */
@@ -326,6 +328,8 @@
        soc {
                compatible = "simple-bus";
                interrupt-parent = <&gic>;
+               bootph-all;
+
                #address-cells = <2>;
                #size-cells = <2>;
                ranges;
@@ -464,6 +468,7 @@
                pfc: pinctrl@e6060000 {
                        compatible = "renesas,pfc-r8a774e1";
                        reg = <0 0xe6060000 0 0x50c>;
+                       bootph-all;
                };
 
                cmt0: timer@e60f0000 {
@@ -544,11 +549,13 @@
                        #clock-cells = <2>;
                        #power-domain-cells = <0>;
                        #reset-cells = <1>;
+                       bootph-all;
                };
 
                rst: reset-controller@e6160000 {
                        compatible = "renesas,r8a774e1-rst";
                        reg = <0 0xe6160000 0 0x0200>;
+                       bootph-all;
                };
 
                sysc: system-controller@e6180000 {
@@ -2917,6 +2924,7 @@
                prr: chipid@fff00044 {
                        compatible = "renesas,prr";
                        reg = <0 0xfff00044 0 4>;
+                       bootph-all;
                };
        };