--- /dev/null
+From db11ebcc198a25cec4b5a7c9c66134ec4db04777 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 6 Sep 2019 16:21:19 +0800
+Subject: ALSA: lx6464es - add support for LX6464ESe pci express variant
+
+From: Tim Blechmann <tim@klingt.org>
+
+[ Upstream commit 789492f0c86505e63369907bcb1afdf52dec9366 ]
+
+The pci express variant of the digigram lx6464es card has a different
+device ID, but works without changes to the driver.
+Thanks to Nikolas Slottke for reporting and testing.
+
+Signed-off-by: Tim Blechmann <tim@klingt.org>
+Link: https://lore.kernel.org/r/20190906082119.40971-1-tim@klingt.org
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/pci_ids.h | 2 ++
+ sound/pci/lx6464es/lx6464es.c | 8 ++++++++
+ 2 files changed, 10 insertions(+)
+
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index 81ddbd891202..bd682fcb9768 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -1952,6 +1952,8 @@
+ #define PCI_VENDOR_ID_DIGIGRAM 0x1369
+ #define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_SERIAL_SUBSYSTEM 0xc001
+ #define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_CAE_SERIAL_SUBSYSTEM 0xc002
++#define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ESE_SERIAL_SUBSYSTEM 0xc021
++#define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ESE_CAE_SERIAL_SUBSYSTEM 0xc022
+
+ #define PCI_VENDOR_ID_KAWASAKI 0x136b
+ #define PCI_DEVICE_ID_MCHIP_KL5A72002 0xff01
+diff --git a/sound/pci/lx6464es/lx6464es.c b/sound/pci/lx6464es/lx6464es.c
+index 54f6252faca6..daf25655f635 100644
+--- a/sound/pci/lx6464es/lx6464es.c
++++ b/sound/pci/lx6464es/lx6464es.c
+@@ -65,6 +65,14 @@ static const struct pci_device_id snd_lx6464es_ids[] = {
+ PCI_VENDOR_ID_DIGIGRAM,
+ PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_CAE_SERIAL_SUBSYSTEM),
+ }, /* LX6464ES-CAE */
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_LX6464ES,
++ PCI_VENDOR_ID_DIGIGRAM,
++ PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ESE_SERIAL_SUBSYSTEM),
++ }, /* LX6464ESe */
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_LX6464ES,
++ PCI_VENDOR_ID_DIGIGRAM,
++ PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ESE_CAE_SERIAL_SUBSYSTEM),
++ }, /* LX6464ESe-CAE */
+ { 0, },
+ };
+
+--
+2.25.1
+
--- /dev/null
+From e698fa5cce9bd9ab5e6c5ba33bf2d07e559d4492 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 6 Nov 2018 20:08:14 +0000
+Subject: hwmon/k10temp, x86/amd_nb: Consolidate shared device IDs
+
+From: Woods, Brian <Brian.Woods@amd.com>
+
+[ Upstream commit dedf7dce4cec5c0abe69f4fa6938d5100398220b ]
+
+Consolidate shared PCI_DEVICE_IDs that were scattered through k10temp
+and amd_nb, and move them into pci_ids.
+
+Signed-off-by: Brian Woods <brian.woods@amd.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Acked-by: Guenter Roeck <linux@roeck-us.net>
+CC: Bjorn Helgaas <bhelgaas@google.com>
+CC: Clemens Ladisch <clemens@ladisch.de>
+CC: "H. Peter Anvin" <hpa@zytor.com>
+CC: Ingo Molnar <mingo@redhat.com>
+CC: Jean Delvare <jdelvare@suse.com>
+CC: Jia Zhang <qianyue.zj@alibaba-inc.com>
+CC: <linux-hwmon@vger.kernel.org>
+CC: <linux-pci@vger.kernel.org>
+CC: Pu Wen <puwen@hygon.cn>
+CC: Thomas Gleixner <tglx@linutronix.de>
+CC: x86-ml <x86@kernel.org>
+Link: http://lkml.kernel.org/r/20181106200754.60722-2-brian.woods@amd.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/kernel/amd_nb.c | 3 +--
+ drivers/hwmon/k10temp.c | 9 +--------
+ include/linux/pci_ids.h | 2 ++
+ 3 files changed, 4 insertions(+), 10 deletions(-)
+
+diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
+index b481b95bd8f6..bf440af5ff9c 100644
+--- a/arch/x86/kernel/amd_nb.c
++++ b/arch/x86/kernel/amd_nb.c
+@@ -11,13 +11,12 @@
+ #include <linux/errno.h>
+ #include <linux/export.h>
+ #include <linux/spinlock.h>
++#include <linux/pci_ids.h>
+ #include <asm/amd_nb.h>
+
+ #define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
+ #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
+-#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
+ #define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
+-#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
+ #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
+
+ /* Protect the PCI config register pairs used for SMN and DF indirect access. */
+diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+index 2cef0c37ff6f..bc6871c8dd4e 100644
+--- a/drivers/hwmon/k10temp.c
++++ b/drivers/hwmon/k10temp.c
+@@ -23,6 +23,7 @@
+ #include <linux/init.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
++#include <linux/pci_ids.h>
+ #include <asm/amd_nb.h>
+ #include <asm/processor.h>
+
+@@ -41,14 +42,6 @@ static DEFINE_MUTEX(nb_smu_ind_mutex);
+ #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
+ #endif
+
+-#ifndef PCI_DEVICE_ID_AMD_17H_DF_F3
+-#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
+-#endif
+-
+-#ifndef PCI_DEVICE_ID_AMD_17H_M10H_DF_F3
+-#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
+-#endif
+-
+ /* CPUID function 0x80000001, ebx */
+ #define CPUID_PKGTYPE_MASK 0xf0000000
+ #define CPUID_PKGTYPE_F 0x00000000
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index 861ee391dc33..857cfd6281a0 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -545,6 +545,8 @@
+ #define PCI_DEVICE_ID_AMD_16H_NB_F4 0x1534
+ #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F3 0x1583
+ #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F4 0x1584
++#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
++#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
+ #define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
+ #define PCI_DEVICE_ID_AMD_LANCE 0x2000
+ #define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
+--
+2.25.1
+
--- /dev/null
+From ecf1288d150d263a59f9cd86dcf8abf6b50c4961 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 25 Mar 2019 15:09:46 +0530
+Subject: misc: pci_endpoint_test: Add support to test PCI EP in AM654x
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Kishon Vijay Abraham I <kishon@ti.com>
+
+[ Upstream commit 5bb04b19230c02cc1b450b029856cbe093e09908 ]
+
+TI's AM654x PCIe EP has a restriction that BAR_0 is mapped to
+application registers. "PCIe Inbound Address Translation" section in
+AM65x Sitara Processors TRM (SPRUID7 – April 2018) describes BAR0 as
+reserved.
+
+Configure pci_endpoint_test to use BAR_2 instead.
+
+Also set alignment to 64K since "PCIe Subsystem Address Translation"
+section in TRM indicates minimum ATU window size is 64K.
+
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/misc/pci_endpoint_test.c | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
+index 2b3d61d565f0..2c472f9cc135 100644
+--- a/drivers/misc/pci_endpoint_test.c
++++ b/drivers/misc/pci_endpoint_test.c
+@@ -75,6 +75,11 @@
+ #define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24
+ #define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
+
++#define PCI_DEVICE_ID_TI_AM654 0xb00c
++
++#define is_am654_pci_dev(pdev) \
++ ((pdev)->device == PCI_DEVICE_ID_TI_AM654)
++
+ static DEFINE_IDA(pci_endpoint_test_ida);
+
+ #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
+@@ -593,6 +598,7 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
+ int ret = -EINVAL;
+ enum pci_barno bar;
+ struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
++ struct pci_dev *pdev = test->pdev;
+
+ mutex_lock(&test->mutex);
+ switch (cmd) {
+@@ -600,6 +606,8 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
+ bar = arg;
+ if (bar < 0 || bar > 5)
+ goto ret;
++ if (is_am654_pci_dev(pdev) && bar == BAR_0)
++ goto ret;
+ ret = pci_endpoint_test_bar(test, bar);
+ break;
+ case PCITEST_LEGACY_IRQ:
+@@ -792,11 +800,20 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev)
+ pci_disable_device(pdev);
+ }
+
++static const struct pci_endpoint_test_data am654_data = {
++ .test_reg_bar = BAR_2,
++ .alignment = SZ_64K,
++ .irq_type = IRQ_TYPE_MSI,
++};
++
+ static const struct pci_device_id pci_endpoint_test_tbl[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
+ { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
+ { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0) },
+ { PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, 0xedda) },
++ { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
++ .driver_data = (kernel_ulong_t)&am654_data
++ },
+ { }
+ };
+ MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
+--
+2.25.1
+
--- /dev/null
+From 66cbc41cb87fd10f8e591aa7f01bab734cef9a1c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 21 Feb 2019 11:16:20 +0800
+Subject: misc: pci_endpoint_test: Add the layerscape EP device support
+
+From: Xiaowei Bao <xiaowei.bao@nxp.com>
+
+[ Upstream commit 85cef374d0ba93b8a2bd24850b97c1b34c666ccb ]
+
+Add the layerscape EP device support in pci_endpoint_test driver.
+
+Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Minghuan Lian <minghuan.lian@nxp.com>
+Reviewed-by: Zhiqiang Hou <zhiqiang.hou@nxp.com>
+Reviewed-by: Greg KH <gregkh@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/misc/pci_endpoint_test.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
+index 727dc6ec427d..2b3d61d565f0 100644
+--- a/drivers/misc/pci_endpoint_test.c
++++ b/drivers/misc/pci_endpoint_test.c
+@@ -795,6 +795,7 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev)
+ static const struct pci_device_id pci_endpoint_test_tbl[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
+ { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
++ { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0) },
+ { PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, 0xedda) },
+ { }
+ };
+--
+2.25.1
+
--- /dev/null
+From 47a4ea62fe1922bda8fe76b071e85e1bebdb9d22 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 28 May 2020 13:57:42 -0700
+Subject: PCI: Add ACS quirk for Intel Root Complex Integrated Endpoints
+
+From: Ashok Raj <ashok.raj@intel.com>
+
+[ Upstream commit 3247bd10a4502a3075ce8e1c3c7d31ef76f193ce ]
+
+All Intel platforms guarantee that all root complex implementations must
+send transactions up to IOMMU for address translations. Hence for Intel
+RCiEP devices, we can assume some ACS-type isolation even without an ACS
+capability.
+
+From the Intel VT-d spec, r3.1, sec 3.16 ("Root-Complex Peer to Peer
+Considerations"):
+
+ When DMA remapping is enabled, peer-to-peer requests through the
+ Root-Complex must be handled as follows:
+
+ - The input address in the request is translated (through first-level,
+ second-level or nested translation) to a host physical address (HPA).
+ The address decoding for peer addresses must be done only on the
+ translated HPA. Hardware implementations are free to further limit
+ peer-to-peer accesses to specific host physical address regions (or
+ to completely disallow peer-forwarding of translated requests).
+
+ - Since address translation changes the contents (address field) of
+ the PCI Express Transaction Layer Packet (TLP), for PCI Express
+ peer-to-peer requests with ECRC, the Root-Complex hardware must use
+ the new ECRC (re-computed with the translated address) if it
+ decides to forward the TLP as a peer request.
+
+ - Root-ports, and multi-function root-complex integrated endpoints, may
+ support additional peer-to-peer control features by supporting PCI
+ Express Access Control Services (ACS) capability. Refer to ACS
+ capability in PCI Express specifications for details.
+
+Since Linux didn't give special treatment to allow this exception, certain
+RCiEP MFD devices were grouped in a single IOMMU group. This doesn't permit
+a single device to be assigned to a guest for instance.
+
+In one vendor system: Device 14.x were grouped in a single IOMMU group.
+
+ /sys/kernel/iommu_groups/5/devices/0000:00:14.0
+ /sys/kernel/iommu_groups/5/devices/0000:00:14.2
+ /sys/kernel/iommu_groups/5/devices/0000:00:14.3
+
+After this patch:
+
+ /sys/kernel/iommu_groups/5/devices/0000:00:14.0
+ /sys/kernel/iommu_groups/5/devices/0000:00:14.2
+ /sys/kernel/iommu_groups/6/devices/0000:00:14.3 <<< new group
+
+14.0 and 14.2 are integrated devices, but legacy end points, whereas 14.3
+was a PCIe-compliant RCiEP.
+
+ 00:14.3 Network controller: Intel Corporation Device 9df0 (rev 30)
+ Capabilities: [40] Express (v2) Root Complex Integrated Endpoint, MSI 00
+
+This permits assigning this device to a guest VM.
+
+[bhelgaas: drop "Fixes" tag since this doesn't fix a bug in that commit]
+Link: https://lore.kernel.org/r/1590699462-7131-1-git-send-email-ashok.raj@intel.com
+Tested-by: Darrel Goeddel <dgoeddel@forcepoint.com>
+Signed-off-by: Ashok Raj <ashok.raj@intel.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
+Cc: stable@vger.kernel.org
+Cc: Lu Baolu <baolu.lu@linux.intel.com>
+Cc: Mark Scott <mscott@forcepoint.com>,
+Cc: Romil Sharma <rsharma@forcepoint.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/quirks.c | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
+index 013b84880e1d..d6236bb26950 100644
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -4543,6 +4543,20 @@ static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
+ return acs_flags ? 0 : 1;
+ }
+
++static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags)
++{
++ /*
++ * Intel RCiEP's are required to allow p2p only on translated
++ * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16,
++ * "Root-Complex Peer to Peer Considerations".
++ */
++ if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END)
++ return -ENOTTY;
++
++ return pci_acs_ctrl_enabled(acs_flags,
++ PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
++}
++
+ static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
+ {
+ /*
+@@ -4626,6 +4640,7 @@ static const struct pci_dev_acs_enabled {
+ /* I219 */
+ { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
+ { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
++ { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs },
+ /* QCOM QDF2xxx root ports */
+ { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
+ { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
+--
+2.25.1
+
--- /dev/null
+From 4672670eed9d3bc03e17be5baeab6a4737879605 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 20 Aug 2019 10:09:45 +0530
+Subject: PCI: Add ACS quirk for iProc PAXB
+
+From: Abhinav Ratna <abhinav.ratna@broadcom.com>
+
+[ Upstream commit 46b2c32df7a462d0e64b68c513e5c4c1b2a399a7 ]
+
+iProc PAXB Root Ports don't advertise an ACS capability, but they do not
+allow peer-to-peer transactions between Root Ports. Add an ACS quirk so
+each Root Port can be in a separate IOMMU group.
+
+[bhelgaas: commit log, comment, use common implementation style]
+Link: https://lore.kernel.org/r/1566275985-25670-1-git-send-email-srinath.mannam@broadcom.com
+Signed-off-by: Abhinav Ratna <abhinav.ratna@broadcom.com>
+Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Scott Branden <scott.branden@broadcom.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/quirks.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
+index 92892b1c35fa..013b84880e1d 100644
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -4543,6 +4543,19 @@ static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
+ return acs_flags ? 0 : 1;
+ }
+
++static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
++{
++ /*
++ * iProc PAXB Root Ports don't advertise an ACS capability, but
++ * they do not allow peer-to-peer transactions between Root Ports.
++ * Allow each Root Port to be in a separate IOMMU group by masking
++ * SV/RR/CR/UF bits.
++ */
++ acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
++
++ return acs_flags ? 0 : 1;
++}
++
+ static const struct pci_dev_acs_enabled {
+ u16 vendor;
+ u16 device;
+@@ -4634,6 +4647,7 @@ static const struct pci_dev_acs_enabled {
+ { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
+ { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
+ { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
++ { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
+ { 0 }
+ };
+
+--
+2.25.1
+
--- /dev/null
+From 74ddda73cc11c36a8364c43d1287174074ba0a3d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 12 Sep 2019 16:00:39 +0300
+Subject: PCI: Add Amazon's Annapurna Labs vendor ID
+
+From: Jonathan Chocron <jonnyc@amazon.com>
+
+[ Upstream commit 4a36a60c34f42f75e8b4f8cd24fcfade26111334 ]
+
+Add Amazon's Annapurna Labs vendor ID to pci_ids.h.
+
+Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Andrew Murray <andrew.murray@arm.com>
+Acked-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/pci_ids.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index 3329387261df..b047b0af530d 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -2576,6 +2576,8 @@
+
+ #define PCI_VENDOR_ID_ASMEDIA 0x1b21
+
++#define PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS 0x1c36
++
+ #define PCI_VENDOR_ID_CIRCUITCO 0x1cc8
+ #define PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD 0x0001
+
+--
+2.25.1
+
--- /dev/null
+From 6c141aefce87d6a0e66b656a2785c1356473b2a5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 27 Aug 2019 08:33:09 +0800
+Subject: PCI: Add Genesys Logic, Inc. Vendor ID
+
+From: Ben Chuang <ben.chuang@genesyslogic.com.tw>
+
+[ Upstream commit 4460d68f0b2f9092273531fbc65613e1855c2e07 ]
+
+Add the Genesys Logic, Inc. vendor ID to pci_ids.h.
+
+Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
+Co-developed-by: Michael K Johnson <johnsonm@danlj.org>
+Signed-off-by: Michael K Johnson <johnsonm@danlj.org>
+Acked-by: Adrian Hunter <adrian.hunter@intel.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/pci_ids.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index bd682fcb9768..3329387261df 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -2409,6 +2409,8 @@
+ #define PCI_DEVICE_ID_RDC_R6061 0x6061
+ #define PCI_DEVICE_ID_RDC_D1010 0x1010
+
++#define PCI_VENDOR_ID_GLI 0x17a0
++
+ #define PCI_VENDOR_ID_LENOVO 0x17aa
+
+ #define PCI_VENDOR_ID_QCOM 0x17cb
+--
+2.25.1
+
--- /dev/null
+From bad9e3d9e260c4728e18356a05cc57af90fab2e6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 10 Mar 2020 20:50:07 +0800
+Subject: PCI: Add Loongson vendor ID
+
+From: Tiezhu Yang <yangtiezhu@loongson.cn>
+
+[ Upstream commit 9acb9fe18d863aacc99948963f8d5d447dc311be ]
+
+Add the Loongson vendor ID to pci_ids.h to be used by the controller
+driver in the future.
+
+The Loongson vendor ID can be found at the following link:
+https://git.kernel.org/pub/scm/utils/pciutils/pciutils.git/tree/pci.ids
+
+Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
+Signed-off-by: Jens Axboe <axboe@kernel.dk>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/pci_ids.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index a81fcb2f2cb7..14baae112a54 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -148,6 +148,8 @@
+
+ /* Vendors and devices. Sort key: vendor first, device next. */
+
++#define PCI_VENDOR_ID_LOONGSON 0x0014
++
+ #define PCI_VENDOR_ID_TTTECH 0x0357
+ #define PCI_DEVICE_ID_TTTECH_MC322 0x000a
+
+--
+2.25.1
+
--- /dev/null
+From 8d18476964be55902ddc047a2e9de926608d7837 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 6 Jun 2019 14:52:25 +0530
+Subject: PCI: Add NVIDIA GPU multi-function power dependencies
+
+From: Abhishek Sahu <abhsahu@nvidia.com>
+
+[ Upstream commit 6d2e369f0d4c3e6125c886847c04106b03d2609e ]
+
+The NVIDIA Turing GPU is a multi-function PCI device with the following
+functions:
+
+ - Function 0: VGA display controller
+ - Function 1: Audio controller
+ - Function 2: USB xHCI Host controller
+ - Function 3: USB Type-C UCSI controller
+
+Function 0 is tightly coupled with other functions in the hardware. When
+function 0 is in D3, it gates power for hardware blocks used by other
+functions, which means those functions only work when function 0 is in D0.
+If any of these functions (1/2/3) are in D0, then function 0 should also be
+in D0.
+
+Commit 07f4f97d7b4b ("vga_switcheroo: Use device link for HDA controller")
+already creates a device link to show the dependency of function 1 on
+function 0 of this GPU. Create additional device links to express the
+dependencies of functions 2 and 3 on function 0. This means function 0
+will be in D0 if any other function is in D0.
+
+[bhelgaas: I think the PCI spec expectation is that functions can be
+power-managed independently, so I don't think this device is technically
+compliant. For example, the PCIe r5.0 spec, sec 1.4, says "the PCI/PCIe
+hardware/software model includes architectural constructs necessary to
+discover, configure, and use a Function, without needing Function-specific
+knowledge" and sec 5.1 says "D states are associated with a particular
+Function" and "PM provides ... a mechanism to identify power management
+capabilities of a given Function [and] the ability to transition a Function
+into a certain power management state."]
+
+Link: https://lore.kernel.org/lkml/20190606092225.17960-3-abhsahu@nvidia.com
+Signed-off-by: Abhishek Sahu <abhsahu@nvidia.com>
+[bhelgaas: commit log]
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/quirks.c | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
+index d6236bb26950..8ac2d5a4a224 100644
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -5094,6 +5094,32 @@ DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
+ DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
+ PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
+
++/*
++ * Create device link for NVIDIA GPU with integrated USB xHCI Host
++ * controller to VGA.
++ */
++static void quirk_gpu_usb(struct pci_dev *usb)
++{
++ pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
++}
++DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
++ PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
++
++/*
++ * Create device link for NVIDIA GPU with integrated Type-C UCSI controller
++ * to VGA. Currently there is no class code defined for UCSI device over PCI
++ * so using UNKNOWN class for now and it will be updated when UCSI
++ * over PCI gets a class code.
++ */
++#define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
++static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
++{
++ pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
++}
++DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
++ PCI_CLASS_SERIAL_UNKNOWN, 8,
++ quirk_gpu_usb_typec_ucsi);
++
+ /*
+ * Some IDT switches incorrectly flag an ACS Source Validation error on
+ * completions for config read requests even though PCIe r4.0, sec
+--
+2.25.1
+
--- /dev/null
+From 7ce579fdbb108a23201f8e78ff3c16d89b5b9034 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 4 Jun 2019 15:29:25 +0200
+Subject: PCI: Add Synopsys endpoint EDDA Device ID
+
+From: Gustavo Pimentel <Gustavo.Pimentel@synopsys.com>
+
+[ Upstream commit 1f418f46503d72594bbe6407d97fd2ae1ce15ee6 ]
+
+Create and add Synopsys Endpoint EDDA Device ID to PCI ID list, since
+this ID is now being use on two different drivers (pci_endpoint_test.ko
+and dw-edma-pcie.ko).
+
+Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
+Acked-by: Bjorn Helgaas <bhelgaas@google.com>
+Cc: Kishon Vijay Abraham I <kishon@ti.com>
+Cc: Bjorn Helgaas <bhelgaas@google.com>
+Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Cc: Joao Pinto <jpinto@synopsys.com>
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/misc/pci_endpoint_test.c | 2 +-
+ include/linux/pci_ids.h | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
+index 2c472f9cc135..7d166f57f624 100644
+--- a/drivers/misc/pci_endpoint_test.c
++++ b/drivers/misc/pci_endpoint_test.c
+@@ -810,7 +810,7 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
+ { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
+ { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0) },
+- { PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, 0xedda) },
++ { PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },
+ { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
+ .driver_data = (kernel_ulong_t)&am654_data
+ },
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index 5c395f52d681..47833d8f8928 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -2366,6 +2366,7 @@
+ #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd
+ #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI 0xabce
+ #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31 0xabcf
++#define PCI_DEVICE_ID_SYNOPSYS_EDDA 0xedda
+
+ #define PCI_VENDOR_ID_USR 0x16ec
+
+--
+2.25.1
+
--- /dev/null
+From e1aa3a04209438197b4a057af138c36d49fdf9c9 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 11 Nov 2018 20:31:21 +0100
+Subject: PCI: add USR vendor id and use it in r8169 and w6692 driver
+
+From: Heiner Kallweit <hkallweit1@gmail.com>
+
+[ Upstream commit 9206eb0bc5679d06d2f54b9db86fe2b9a55e07e4 ]
+
+The PCI vendor id of U.S. Robotics isn't defined in pci_ids.h so far,
+only ISDN driver w6692 has a private definition. Move the definition
+to pci_ids.h and use it in the r8169 driver too.
+
+Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/isdn/hardware/mISDN/w6692.c | 3 ---
+ drivers/net/ethernet/realtek/r8169.c | 2 +-
+ include/linux/pci_ids.h | 2 ++
+ 3 files changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/isdn/hardware/mISDN/w6692.c b/drivers/isdn/hardware/mISDN/w6692.c
+index 5acf6ab67cd3..6f60aced11c5 100644
+--- a/drivers/isdn/hardware/mISDN/w6692.c
++++ b/drivers/isdn/hardware/mISDN/w6692.c
+@@ -52,10 +52,7 @@ static const struct w6692map w6692_map[] =
+ {W6692_USR, "USR W6692"}
+ };
+
+-#ifndef PCI_VENDOR_ID_USR
+-#define PCI_VENDOR_ID_USR 0x16ec
+ #define PCI_DEVICE_ID_USR_6692 0x3409
+-#endif
+
+ struct w6692_ch {
+ struct bchannel bch;
+diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
+index 807ef43a3cda..6df404e3dd27 100644
+--- a/drivers/net/ethernet/realtek/r8169.c
++++ b/drivers/net/ethernet/realtek/r8169.c
+@@ -229,7 +229,7 @@ static const struct pci_device_id rtl8169_pci_tbl[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
+ { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
+ { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
+- { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
++ { PCI_DEVICE(PCI_VENDOR_ID_USR, 0x0116), 0, 0, RTL_CFG_0 },
+ { PCI_VENDOR_ID_LINKSYS, 0x1032,
+ PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
+ { 0x0001, 0x8168,
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index 81c7af243a31..2792bca03088 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -2362,6 +2362,8 @@
+
+ #define PCI_VENDOR_ID_SYNOPSYS 0x16c3
+
++#define PCI_VENDOR_ID_USR 0x16ec
++
+ #define PCI_VENDOR_ID_VITESSE 0x1725
+ #define PCI_DEVICE_ID_VITESSE_VSC7174 0x7174
+
+--
+2.25.1
+
--- /dev/null
+From 1942a42ef3e4fde12ff48924d15a093fe5088234 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 20 May 2020 18:23:30 -0500
+Subject: PCI: Avoid FLR for AMD Matisse HD Audio & USB 3.0
+
+From: Marcos Scriven <marcos@scriven.org>
+
+[ Upstream commit 0d14f06cd6657ba3446a5eb780672da487b068e7 ]
+
+The AMD Matisse HD Audio & USB 3.0 devices advertise Function Level Reset
+support, but hang when an FLR is triggered.
+
+To reproduce the problem, attach the device to a VM, then detach and try to
+attach again.
+
+Rename the existing quirk_intel_no_flr(), which was not Intel-specific, to
+quirk_no_flr(), and apply it to prevent the use of FLR on these AMD
+devices.
+
+Link: https://lore.kernel.org/r/CAAri2DpkcuQZYbT6XsALhx2e6vRqPHwtbjHYeiH7MNp4zmt1RA@mail.gmail.com
+Signed-off-by: Marcos Scriven <marcos@scriven.org>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/quirks.c | 18 ++++++++++++++----
+ 1 file changed, 14 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
+index fb061e1bc084..7a835c49409e 100644
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -4956,13 +4956,23 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
+ }
+ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
+
+-/* FLR may cause some 82579 devices to hang */
+-static void quirk_intel_no_flr(struct pci_dev *dev)
++/*
++ * FLR may cause the following to devices to hang:
++ *
++ * AMD Starship/Matisse HD Audio Controller 0x1487
++ * AMD Matisse USB 3.0 Host Controller 0x149c
++ * Intel 82579LM Gigabit Ethernet Controller 0x1502
++ * Intel 82579V Gigabit Ethernet Controller 0x1503
++ *
++ */
++static void quirk_no_flr(struct pci_dev *dev)
+ {
+ dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
+ }
+-DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr);
+-DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr);
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
+
+ static void quirk_no_ext_tags(struct pci_dev *pdev)
+ {
+--
+2.25.1
+
--- /dev/null
+From 20b895143475b45cd63fb3a1c43fa703a82d5bf0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 24 May 2020 00:35:29 -0700
+Subject: PCI: Avoid FLR for AMD Starship USB 3.0
+
+From: Kevin Buettner <kevinb@redhat.com>
+
+[ Upstream commit 5727043c73fdfe04597971b5f3f4850d879c1f4f ]
+
+The AMD Starship USB 3.0 host controller advertises Function Level Reset
+support, but it apparently doesn't work. Add a quirk to prevent use of FLR
+on this device.
+
+Without this quirk, when attempting to assign (pass through) an AMD
+Starship USB 3.0 host controller to a guest OS, the system becomes
+increasingly unresponsive over the course of several minutes, eventually
+requiring a hard reset. Shortly after attempting to start the guest, I see
+these messages:
+
+ vfio-pci 0000:05:00.3: not ready 1023ms after FLR; waiting
+ vfio-pci 0000:05:00.3: not ready 2047ms after FLR; waiting
+ vfio-pci 0000:05:00.3: not ready 4095ms after FLR; waiting
+ vfio-pci 0000:05:00.3: not ready 8191ms after FLR; waiting
+
+And then eventually:
+
+ vfio-pci 0000:05:00.3: not ready 65535ms after FLR; giving up
+ INFO: NMI handler (perf_event_nmi_handler) took too long to run: 0.000 msecs
+ perf: interrupt took too long (642744 > 2500), lowering kernel.perf_event_max_sample_rate to 1000
+ INFO: NMI handler (perf_event_nmi_handler) took too long to run: 82.270 msecs
+ INFO: NMI handler (perf_event_nmi_handler) took too long to run: 680.608 msecs
+ INFO: NMI handler (perf_event_nmi_handler) took too long to run: 100.952 msecs
+ ...
+ watchdog: BUG: soft lockup - CPU#3 stuck for 22s! [qemu-system-x86:7487]
+
+Tested on a Micro-Star International Co., Ltd. MS-7C59/Creator TRX40
+motherboard with an AMD Ryzen Threadripper 3970X.
+
+Link: https://lore.kernel.org/r/20200524003529.598434ff@f31-4.lan
+Signed-off-by: Kevin Buettner <kevinb@redhat.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/quirks.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
+index 7a835c49409e..92892b1c35fa 100644
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -4960,6 +4960,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
+ * FLR may cause the following to devices to hang:
+ *
+ * AMD Starship/Matisse HD Audio Controller 0x1487
++ * AMD Starship USB 3.0 Host Controller 0x148c
+ * AMD Matisse USB 3.0 Host Controller 0x149c
+ * Intel 82579LM Gigabit Ethernet Controller 0x1502
+ * Intel 82579V Gigabit Ethernet Controller 0x1503
+@@ -4970,6 +4971,7 @@ static void quirk_no_flr(struct pci_dev *dev)
+ dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
+ }
+ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
+ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
+ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
+ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
+--
+2.25.1
+
--- /dev/null
+From 72e1f49e14d5f69c12a70468e4dfb66523e1dba5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 8 May 2020 14:53:41 +0800
+Subject: PCI: Avoid Pericom USB controller OHCI/EHCI PME# defect
+
+From: Kai-Heng Feng <kai.heng.feng@canonical.com>
+
+[ Upstream commit 68f5fc4ea9ddf9f77720d568144219c4e6452cde ]
+
+Both Pericom OHCI and EHCI devices advertise PME# support from all power
+states:
+
+ 06:00.0 USB controller [0c03]: Pericom Semiconductor PI7C9X442SL USB OHCI Controller [12d8:400e] (rev 01) (prog-if 10 [OHCI])
+ Subsystem: Pericom Semiconductor PI7C9X442SL USB OHCI Controller [12d8:400e]
+ Capabilities: [80] Power Management version 3
+ Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
+
+ 06:00.2 USB controller [0c03]: Pericom Semiconductor PI7C9X442SL USB EHCI Controller [12d8:400f] (rev 01) (prog-if 20 [EHCI])
+ Subsystem: Pericom Semiconductor PI7C9X442SL USB EHCI Controller [12d8:400f]
+ Capabilities: [80] Power Management version 3
+ Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
+
+But testing shows that it's unreliable: there is a 20% chance PME# won't be
+asserted when a USB device is plugged.
+
+Remove PME support for both devices to make USB plugging work reliably.
+
+Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=205981
+Link: https://lore.kernel.org/r/20200508065343.32751-2-kai.heng.feng@canonical.com
+Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/quirks.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
+index ca41cff2e68c..fb061e1bc084 100644
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -5294,6 +5294,19 @@ static void pci_fixup_no_d0_pme(struct pci_dev *dev)
+ }
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
+
++/*
++ * Device [12d8:0x400e] and [12d8:0x400f]
++ * These devices advertise PME# support in all power states but don't
++ * reliably assert it.
++ */
++static void pci_fixup_no_pme(struct pci_dev *dev)
++{
++ pci_info(dev, "PME# is unreliable, disabling it\n");
++ dev->pme_support = 0;
++}
++DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_pme);
++DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_pme);
++
+ static void apex_pci_fixup_class(struct pci_dev *pdev)
+ {
+ pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class;
+--
+2.25.1
+
--- /dev/null
+From ece493bfa76e57f3a2f438d99314744cba7abccf Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 8 Jul 2019 13:17:44 +0800
+Subject: PCI: Enable NVIDIA HDA controllers
+
+From: Lukas Wunner <lukas@wunner.de>
+
+[ Upstream commit b516ea586d717472178e6ef1c152e85608b0ce32 ]
+
+Many NVIDIA GPUs can be configured as either a single-function video device
+or a multi-function device with video at function 0 and an HDA audio
+controller at function 1. The HDA controller can be enabled or disabled by
+a bit in the function 0 config space.
+
+Some BIOSes leave the HDA disabled, which means the HDMI connector from the
+NVIDIA GPU may not work. Sometimes the BIOS enables the HDA if an HDMI
+cable is connected at boot time, but that doesn't handle hotplug cases.
+
+Enable the HDA controller on device enumeration and resume and re-read the
+header type, which tells us whether the GPU is a multi-function device.
+
+This quirk is limited to NVIDIA PCI devices with the VGA Controller device
+class. This is expected to correspond to product configurations where the
+NVIDIA GPU has connectors attached. Other products where the device class
+is 3D Controller are expected to correspond to configurations where the
+NVIDIA GPU is dedicated (dGPU) and has no connectors. See original post
+(URL below) for more details.
+
+This commit takes inspiration from an earlier patch by Daniel Drake.
+
+Link: https://lore.kernel.org/r/20190708051744.24039-1-drake@endlessm.com v2
+Link: https://lore.kernel.org/r/20190613063514.15317-1-drake@endlessm.com v1
+Link: https://devtalk.nvidia.com/default/topic/1024022
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75985
+Signed-off-by: Lukas Wunner <lukas@wunner.de>
+Signed-off-by: Daniel Drake <drake@endlessm.com>
+[bhelgaas: commit log, log message, return early if already enabled]
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Cc: Aaron Plattner <aplattner@nvidia.com>
+Cc: Peter Wu <peter@lekensteyn.nl>
+Cc: Ilia Mirkin <imirkin@alum.mit.edu>
+Cc: Karol Herbst <kherbst@redhat.com>
+Cc: Maik Freudenberg <hhfeuer@gmx.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/quirks.c | 30 ++++++++++++++++++++++++++++++
+ include/linux/pci_ids.h | 1 +
+ 2 files changed, 31 insertions(+)
+
+diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
+index 8ac2d5a4a224..502dca568d6c 100644
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -5120,6 +5120,36 @@ DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
+ PCI_CLASS_SERIAL_UNKNOWN, 8,
+ quirk_gpu_usb_typec_ucsi);
+
++/*
++ * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
++ * disabled. https://devtalk.nvidia.com/default/topic/1024022
++ */
++static void quirk_nvidia_hda(struct pci_dev *gpu)
++{
++ u8 hdr_type;
++ u32 val;
++
++ /* There was no integrated HDA controller before MCP89 */
++ if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
++ return;
++
++ /* Bit 25 at offset 0x488 enables the HDA controller */
++ pci_read_config_dword(gpu, 0x488, &val);
++ if (val & BIT(25))
++ return;
++
++ pci_info(gpu, "Enabling HDA controller\n");
++ pci_write_config_dword(gpu, 0x488, val | BIT(25));
++
++ /* The GPU becomes a multi-function device when the HDA is enabled */
++ pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
++ gpu->multifunction = !!(hdr_type & 0x80);
++}
++DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
++ PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
++DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
++ PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
++
+ /*
+ * Some IDT switches incorrectly flag an ACS Source Validation error on
+ * completions for config read requests even though PCIe r4.0, sec
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index 47833d8f8928..b952f1557f5d 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -1336,6 +1336,7 @@
+ #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP78S_SMBUS 0x0752
+ #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE 0x0759
+ #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_SMBUS 0x07D8
++#define PCI_DEVICE_ID_NVIDIA_GEFORCE_320M 0x08A0
+ #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS 0x0AA2
+ #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA 0x0D85
+
+--
+2.25.1
+
--- /dev/null
+From bbdc04aec026803bbb9a4b208f0a59b9b67eeb67 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 6 Jun 2019 14:52:24 +0530
+Subject: PCI: Generalize multi-function power dependency device links
+
+From: Abhishek Sahu <abhsahu@nvidia.com>
+
+[ Upstream commit a17beb1a0882a544523dcb5d0da4801272dfd43a ]
+
+Although not allowed by the PCI specs, some multi-function devices have
+power dependencies between the functions. For example, function 1 may not
+work unless function 0 is in the D0 power state.
+
+The existing quirk_gpu_hda() adds a device link to express this dependency
+for GPU and HDA devices, but it really is not specific to those device
+types.
+
+Generalize it and rename it to pci_create_device_link() so we can create
+dependencies between any "consumer" and "producer" functions of a
+multi-function device, where the consumer is only functional if the
+producer is in D0. This reorganization should not affect any
+functionality.
+
+Link: https://lore.kernel.org/lkml/20190606092225.17960-2-abhsahu@nvidia.com
+Signed-off-by: Abhishek Sahu <abhsahu@nvidia.com>
+[bhelgaas: commit log, reword diagnostic]
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/quirks.c | 54 ++++++++++++++++++++++++++++----------------
+ 1 file changed, 34 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
+index 0704025a2160..0862cb633849 100644
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -5077,35 +5077,49 @@ static void quirk_fsl_no_msi(struct pci_dev *pdev)
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
+
+ /*
+- * GPUs with integrated HDA controller for streaming audio to attached displays
+- * need a device link from the HDA controller (consumer) to the GPU (supplier)
+- * so that the GPU is powered up whenever the HDA controller is accessed.
+- * The GPU and HDA controller are functions 0 and 1 of the same PCI device.
+- * The device link stays in place until shutdown (or removal of the PCI device
+- * if it's hotplugged). Runtime PM is allowed by default on the HDA controller
+- * to prevent it from permanently keeping the GPU awake.
++ * Although not allowed by the spec, some multi-function devices have
++ * dependencies of one function (consumer) on another (supplier). For the
++ * consumer to work in D0, the supplier must also be in D0. Create a
++ * device link from the consumer to the supplier to enforce this
++ * dependency. Runtime PM is allowed by default on the consumer to prevent
++ * it from permanently keeping the supplier awake.
+ */
+-static void quirk_gpu_hda(struct pci_dev *hda)
++static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
++ unsigned int supplier, unsigned int class,
++ unsigned int class_shift)
+ {
+- struct pci_dev *gpu;
++ struct pci_dev *supplier_pdev;
+
+- if (PCI_FUNC(hda->devfn) != 1)
++ if (PCI_FUNC(pdev->devfn) != consumer)
+ return;
+
+- gpu = pci_get_domain_bus_and_slot(pci_domain_nr(hda->bus),
+- hda->bus->number,
+- PCI_DEVFN(PCI_SLOT(hda->devfn), 0));
+- if (!gpu || (gpu->class >> 16) != PCI_BASE_CLASS_DISPLAY) {
+- pci_dev_put(gpu);
++ supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
++ pdev->bus->number,
++ PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
++ if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
++ pci_dev_put(supplier_pdev);
+ return;
+ }
+
+- if (!device_link_add(&hda->dev, &gpu->dev,
+- DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
+- pci_err(hda, "cannot link HDA to GPU %s\n", pci_name(gpu));
++ if (device_link_add(&pdev->dev, &supplier_pdev->dev,
++ DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
++ pci_info(pdev, "D0 power state depends on %s\n",
++ pci_name(supplier_pdev));
++ else
++ pci_err(pdev, "Cannot enforce power dependency on %s\n",
++ pci_name(supplier_pdev));
++
++ pm_runtime_allow(&pdev->dev);
++ pci_dev_put(supplier_pdev);
++}
+
+- pm_runtime_allow(&hda->dev);
+- pci_dev_put(gpu);
++/*
++ * Create device link for GPUs with integrated HDA controller for streaming
++ * audio to attached displays.
++ */
++static void quirk_gpu_hda(struct pci_dev *hda)
++{
++ pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
+ }
+ DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
+ PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
+--
+2.25.1
+
--- /dev/null
+From 60a56b2359f9809749d033366f077bc0aeeddc95 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 26 Feb 2018 12:49:16 -0600
+Subject: pci:ipmi: Move IPMI PCI class id defines to pci_ids.h
+
+From: Corey Minyard <cminyard@mvista.com>
+
+[ Upstream commit 05c3d056086a6217a77937b7fa0df35ec75715e6 ]
+
+Signed-off-by: Corey Minyard <cminyard@mvista.com>
+Acked-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/char/ipmi/ipmi_si_pci.c | 5 -----
+ include/linux/pci_ids.h | 4 ++++
+ 2 files changed, 4 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/char/ipmi/ipmi_si_pci.c b/drivers/char/ipmi/ipmi_si_pci.c
+index 022e03634ce2..9e9700b1a8e6 100644
+--- a/drivers/char/ipmi/ipmi_si_pci.c
++++ b/drivers/char/ipmi/ipmi_si_pci.c
+@@ -18,11 +18,6 @@ module_param_named(trypci, si_trypci, bool, 0);
+ MODULE_PARM_DESC(trypci, "Setting this to zero will disable the"
+ " default scan of the interfaces identified via pci");
+
+-#define PCI_CLASS_SERIAL_IPMI 0x0c07
+-#define PCI_CLASS_SERIAL_IPMI_SMIC 0x0c0700
+-#define PCI_CLASS_SERIAL_IPMI_KCS 0x0c0701
+-#define PCI_CLASS_SERIAL_IPMI_BT 0x0c0702
+-
+ #define PCI_DEVICE_ID_HP_MMC 0x121A
+
+ static void ipmi_pci_cleanup(struct si_sm_io *io)
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index f4e278493f5b..861ee391dc33 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -117,6 +117,10 @@
+ #define PCI_CLASS_SERIAL_USB_DEVICE 0x0c03fe
+ #define PCI_CLASS_SERIAL_FIBER 0x0c04
+ #define PCI_CLASS_SERIAL_SMBUS 0x0c05
++#define PCI_CLASS_SERIAL_IPMI 0x0c07
++#define PCI_CLASS_SERIAL_IPMI_SMIC 0x0c0700
++#define PCI_CLASS_SERIAL_IPMI_KCS 0x0c0701
++#define PCI_CLASS_SERIAL_IPMI_BT 0x0c0702
+
+ #define PCI_BASE_CLASS_WIRELESS 0x0d
+ #define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10
+--
+2.25.1
+
--- /dev/null
+From 3bf02abe63c92e6d5d564b6baaf535b045e652d1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 5 Sep 2019 17:54:42 -0500
+Subject: PCI: Make ACS quirk implementations more uniform
+
+From: Bjorn Helgaas <bhelgaas@google.com>
+
+[ Upstream commit c8de8ed2dcaac82e5d76d467dc0b02e0ee79809b ]
+
+The ACS quirks differ in needless ways, which makes them look more
+different than they really are.
+
+Reorder the ACS flags in order of definitions in the spec:
+
+ PCI_ACS_SV Source Validation
+ PCI_ACS_TB Translation Blocking
+ PCI_ACS_RR P2P Request Redirect
+ PCI_ACS_CR P2P Completion Redirect
+ PCI_ACS_UF Upstream Forwarding
+ PCI_ACS_EC P2P Egress Control
+ PCI_ACS_DT Direct Translated P2P
+
+(PCIe r5.0, sec 7.7.8.2) and use similar code structure in all. No
+functional change intended.
+
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
+Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/quirks.c | 41 +++++++++++++++++++----------------------
+ 1 file changed, 19 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
+index 502dca568d6c..ae62c0b058dd 100644
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -4333,18 +4333,18 @@ static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
+
+ static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
+ {
++ if (!pci_quirk_cavium_acs_match(dev))
++ return -ENOTTY;
++
+ /*
+- * Cavium root ports don't advertise an ACS capability. However,
++ * Cavium Root Ports don't advertise an ACS capability. However,
+ * the RTL internally implements similar protection as if ACS had
+- * Request Redirection, Completion Redirection, Source Validation,
++ * Source Validation, Request Redirection, Completion Redirection,
+ * and Upstream Forwarding features enabled. Assert that the
+ * hardware implements and enables equivalent ACS functionality for
+ * these flags.
+ */
+- acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);
+-
+- if (!pci_quirk_cavium_acs_match(dev))
+- return -ENOTTY;
++ acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+
+ return acs_flags ? 0 : 1;
+ }
+@@ -4362,7 +4362,7 @@ static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
+ }
+
+ /*
+- * Many Intel PCH root ports do provide ACS-like features to disable peer
++ * Many Intel PCH Root Ports do provide ACS-like features to disable peer
+ * transactions and validate bus numbers in requests, but do not provide an
+ * actual PCIe ACS capability. This is the list of device IDs known to fall
+ * into that category as provided by Intel in Red Hat bugzilla 1037684.
+@@ -4410,37 +4410,34 @@ static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
+ return false;
+ }
+
+-#define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
++#define INTEL_PCH_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
+
+ static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
+ {
+- u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
+- INTEL_PCH_ACS_FLAGS : 0;
+-
+ if (!pci_quirk_intel_pch_acs_match(dev))
+ return -ENOTTY;
+
+- return acs_flags & ~flags ? 0 : 1;
++ if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
++ acs_flags &= ~(INTEL_PCH_ACS_FLAGS);
++
++ return acs_flags ? 0 : 1;
+ }
+
+ /*
+- * These QCOM root ports do provide ACS-like features to disable peer
++ * These QCOM Root Ports do provide ACS-like features to disable peer
+ * transactions and validate bus numbers in requests, but do not provide an
+ * actual PCIe ACS capability. Hardware supports source validation but it
+ * will report the issue as Completer Abort instead of ACS Violation.
+- * Hardware doesn't support peer-to-peer and each root port is a root
+- * complex with unique segment numbers. It is not possible for one root
+- * port to pass traffic to another root port. All PCIe transactions are
+- * terminated inside the root port.
++ * Hardware doesn't support peer-to-peer and each Root Port is a Root
++ * Complex with unique segment numbers. It is not possible for one Root
++ * Port to pass traffic to another Root Port. All PCIe transactions are
++ * terminated inside the Root Port.
+ */
+ static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
+ {
+- u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
+- int ret = acs_flags & ~flags ? 0 : 1;
+-
+- pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret);
++ acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+
+- return ret;
++ return acs_flags ? 0 : 1;
+ }
+
+ /*
+--
+2.25.1
+
--- /dev/null
+From 42e107496b4f4ef6a96f4809852e16ce23a95aee Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 28 Jun 2019 15:34:25 +0800
+Subject: PCI: mediatek: Add controller support for MT7629
+
+From: Jianjun Wang <jianjun.wang@mediatek.com>
+
+[ Upstream commit 0cccd42e6193e168cbecc271dae464e4a53fd7b3 ]
+
+MT7629 is an ARM platform SoC which has the same PCIe IP as MT7622.
+
+The HW default value of its PCI host controller Device ID is invalid,
+fix it to match the hardware implementation.
+
+Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
+[lorenzo.pieralisi@arm.com: commit log/minor spelling update]
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Reviewed-by: Andrew Murray <andrew.murray@arm.com>
+Acked-by: Ryder Lee <ryder.lee@mediatek.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/controller/pcie-mediatek.c | 18 ++++++++++++++++++
+ include/linux/pci_ids.h | 1 +
+ 2 files changed, 19 insertions(+)
+
+diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
+index 1bfbceb9f445..ca06d8bc01e7 100644
+--- a/drivers/pci/controller/pcie-mediatek.c
++++ b/drivers/pci/controller/pcie-mediatek.c
+@@ -72,6 +72,7 @@
+ #define PCIE_MSI_VECTOR 0x0c0
+
+ #define PCIE_CONF_VEND_ID 0x100
++#define PCIE_CONF_DEVICE_ID 0x102
+ #define PCIE_CONF_CLASS_ID 0x106
+
+ #define PCIE_INT_MASK 0x420
+@@ -134,12 +135,16 @@ struct mtk_pcie_port;
+ /**
+ * struct mtk_pcie_soc - differentiate between host generations
+ * @need_fix_class_id: whether this host's class ID needed to be fixed or not
++ * @need_fix_device_id: whether this host's device ID needed to be fixed or not
++ * @device_id: device ID which this host need to be fixed
+ * @ops: pointer to configuration access functions
+ * @startup: pointer to controller setting functions
+ * @setup_irq: pointer to initialize IRQ functions
+ */
+ struct mtk_pcie_soc {
+ bool need_fix_class_id;
++ bool need_fix_device_id;
++ unsigned int device_id;
+ struct pci_ops *ops;
+ int (*startup)(struct mtk_pcie_port *port);
+ int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
+@@ -678,6 +683,9 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
+ writew(val, port->base + PCIE_CONF_CLASS_ID);
+ }
+
++ if (soc->need_fix_device_id)
++ writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);
++
+ /* 100ms timeout value should be enough for Gen1/2 training */
+ err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
+ !!(val & PCIE_PORT_LINKUP_V2), 20,
+@@ -1213,11 +1221,21 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {
+ .setup_irq = mtk_pcie_setup_irq,
+ };
+
++static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {
++ .need_fix_class_id = true,
++ .need_fix_device_id = true,
++ .device_id = PCI_DEVICE_ID_MEDIATEK_7629,
++ .ops = &mtk_pcie_ops_v2,
++ .startup = mtk_pcie_startup_port_v2,
++ .setup_irq = mtk_pcie_setup_irq,
++};
++
+ static const struct of_device_id mtk_pcie_ids[] = {
+ { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
+ { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
+ { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
+ { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
++ { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
+ {},
+ };
+
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index b952f1557f5d..a7abaaa9bc27 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -2132,6 +2132,7 @@
+ #define PCI_VENDOR_ID_MYRICOM 0x14c1
+
+ #define PCI_VENDOR_ID_MEDIATEK 0x14c3
++#define PCI_DEVICE_ID_MEDIATEK_7629 0x7629
+
+ #define PCI_VENDOR_ID_TITAN 0x14D2
+ #define PCI_DEVICE_ID_TITAN_010L 0x8001
+--
+2.25.1
+
--- /dev/null
+From 929b293a664a3acfaaf409a0c37b5a352488b434 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 1 Feb 2019 17:24:52 -0600
+Subject: PCI: Move Rohm Vendor ID to generic list
+
+From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+
+[ Upstream commit 0ce26a1c31ca928df4dfc7504c8898b71ff9f5d5 ]
+
+Move the Rohm Vendor ID to pci_ids.h instead of defining it in several
+drivers.
+
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Mark Brown <broonie@kernel.org>
+Acked-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/dma/pch_dma.c | 1 -
+ drivers/gpio/gpio-ml-ioh.c | 2 --
+ drivers/gpio/gpio-pch.c | 1 -
+ drivers/i2c/busses/i2c-eg20t.c | 1 -
+ drivers/misc/pch_phub.c | 1 -
+ drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 7 ++-----
+ drivers/spi/spi-topcliff-pch.c | 1 -
+ drivers/tty/serial/pch_uart.c | 2 --
+ drivers/usb/gadget/udc/pch_udc.c | 1 -
+ include/linux/pci_ids.h | 2 ++
+ 10 files changed, 4 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/dma/pch_dma.c b/drivers/dma/pch_dma.c
+index 6e91584c3677..47c6e3ceac4d 100644
+--- a/drivers/dma/pch_dma.c
++++ b/drivers/dma/pch_dma.c
+@@ -972,7 +972,6 @@ static void pch_dma_remove(struct pci_dev *pdev)
+ }
+
+ /* PCI Device ID of DMA device */
+-#define PCI_VENDOR_ID_ROHM 0x10DB
+ #define PCI_DEVICE_ID_EG20T_PCH_DMA_8CH 0x8810
+ #define PCI_DEVICE_ID_EG20T_PCH_DMA_4CH 0x8815
+ #define PCI_DEVICE_ID_ML7213_DMA1_8CH 0x8026
+diff --git a/drivers/gpio/gpio-ml-ioh.c b/drivers/gpio/gpio-ml-ioh.c
+index 51c7d1b84c2e..0c076dce9e17 100644
+--- a/drivers/gpio/gpio-ml-ioh.c
++++ b/drivers/gpio/gpio-ml-ioh.c
+@@ -31,8 +31,6 @@
+
+ #define IOH_IRQ_BASE 0
+
+-#define PCI_VENDOR_ID_ROHM 0x10DB
+-
+ struct ioh_reg_comn {
+ u32 ien;
+ u32 istatus;
+diff --git a/drivers/gpio/gpio-pch.c b/drivers/gpio/gpio-pch.c
+index ffce0ab912ed..8c7f3d20e30e 100644
+--- a/drivers/gpio/gpio-pch.c
++++ b/drivers/gpio/gpio-pch.c
+@@ -524,7 +524,6 @@ static int pch_gpio_resume(struct pci_dev *pdev)
+ #define pch_gpio_resume NULL
+ #endif
+
+-#define PCI_VENDOR_ID_ROHM 0x10DB
+ static const struct pci_device_id pch_gpio_pcidev_id[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
+ { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
+diff --git a/drivers/i2c/busses/i2c-eg20t.c b/drivers/i2c/busses/i2c-eg20t.c
+index 835d54ac2971..231675b10376 100644
+--- a/drivers/i2c/busses/i2c-eg20t.c
++++ b/drivers/i2c/busses/i2c-eg20t.c
+@@ -177,7 +177,6 @@ static wait_queue_head_t pch_event;
+ static DEFINE_MUTEX(pch_mutex);
+
+ /* Definition for ML7213 by LAPIS Semiconductor */
+-#define PCI_VENDOR_ID_ROHM 0x10DB
+ #define PCI_DEVICE_ID_ML7213_I2C 0x802D
+ #define PCI_DEVICE_ID_ML7223_I2C 0x8010
+ #define PCI_DEVICE_ID_ML7831_I2C 0x8817
+diff --git a/drivers/misc/pch_phub.c b/drivers/misc/pch_phub.c
+index 540845651b8c..309703e9c42e 100644
+--- a/drivers/misc/pch_phub.c
++++ b/drivers/misc/pch_phub.c
+@@ -64,7 +64,6 @@
+ #define CLKCFG_UARTCLKSEL (1 << 18)
+
+ /* Macros for ML7213 */
+-#define PCI_VENDOR_ID_ROHM 0x10db
+ #define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A
+
+ /* Macros for ML7223 */
+diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+index 43c0c10dfeb7..3a4225837049 100644
+--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
++++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+@@ -27,7 +27,6 @@
+ #define DRV_VERSION "1.01"
+ const char pch_driver_version[] = DRV_VERSION;
+
+-#define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802 /* Pci device ID */
+ #define PCH_GBE_MAR_ENTRIES 16
+ #define PCH_GBE_SHORT_PKT 64
+ #define DSC_INIT16 0xC000
+@@ -37,11 +36,9 @@ const char pch_driver_version[] = DRV_VERSION;
+ #define PCH_GBE_PCI_BAR 1
+ #define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */
+
+-/* Macros for ML7223 */
+-#define PCI_VENDOR_ID_ROHM 0x10db
+-#define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013
++#define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802
+
+-/* Macros for ML7831 */
++#define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013
+ #define PCI_DEVICE_ID_ROHM_ML7831_GBE 0x8802
+
+ #define PCH_GBE_TX_WEIGHT 64
+diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
+index fa730a871d25..8a5966963834 100644
+--- a/drivers/spi/spi-topcliff-pch.c
++++ b/drivers/spi/spi-topcliff-pch.c
+@@ -92,7 +92,6 @@
+ #define PCH_MAX_SPBR 1023
+
+ /* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */
+-#define PCI_VENDOR_ID_ROHM 0x10DB
+ #define PCI_DEVICE_ID_ML7213_SPI 0x802c
+ #define PCI_DEVICE_ID_ML7223_SPI 0x800F
+ #define PCI_DEVICE_ID_ML7831_SPI 0x8816
+diff --git a/drivers/tty/serial/pch_uart.c b/drivers/tty/serial/pch_uart.c
+index 3245cdbf9116..e5ff30544bd0 100644
+--- a/drivers/tty/serial/pch_uart.c
++++ b/drivers/tty/serial/pch_uart.c
+@@ -192,8 +192,6 @@ enum {
+ #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
+ #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
+
+-#define PCI_VENDOR_ID_ROHM 0x10DB
+-
+ #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
+
+ #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
+diff --git a/drivers/usb/gadget/udc/pch_udc.c b/drivers/usb/gadget/udc/pch_udc.c
+index 991184b8bb41..667011c99372 100644
+--- a/drivers/usb/gadget/udc/pch_udc.c
++++ b/drivers/usb/gadget/udc/pch_udc.c
+@@ -368,7 +368,6 @@ struct pch_udc_dev {
+ #define PCI_DEVICE_ID_INTEL_QUARK_X1000_UDC 0x0939
+ #define PCI_DEVICE_ID_INTEL_EG20T_UDC 0x8808
+
+-#define PCI_VENDOR_ID_ROHM 0x10DB
+ #define PCI_DEVICE_ID_ML7213_IOH_UDC 0x801D
+ #define PCI_DEVICE_ID_ML7831_IOH_UDC 0x8808
+
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index 05705d0b5689..5c395f52d681 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -1140,6 +1140,8 @@
+ #define PCI_VENDOR_ID_TCONRAD 0x10da
+ #define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508
+
++#define PCI_VENDOR_ID_ROHM 0x10db
++
+ #define PCI_VENDOR_ID_NVIDIA 0x10de
+ #define PCI_DEVICE_ID_NVIDIA_TNT 0x0020
+ #define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028
+--
+2.25.1
+
--- /dev/null
+From b3b9c51fdcdd2998b2c9cdc9ee691430b55b9d4c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 10 Dec 2018 14:07:54 -0800
+Subject: PCI: Move Synopsys HAPS platform device IDs
+
+From: Thinh Nguyen <thinh.nguyen@synopsys.com>
+
+[ Upstream commit b6061b1e566d70c7686d194a6c47dc6ffa665c77 ]
+
+Move Synopsys HAPS platform device IDs to pci_ids.h so that both
+drivers/pci/quirks.c and dwc3-haps driver can reference these IDs.
+
+Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/usb/dwc3/dwc3-haps.c | 4 ----
+ include/linux/pci_ids.h | 3 +++
+ 2 files changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/usb/dwc3/dwc3-haps.c b/drivers/usb/dwc3/dwc3-haps.c
+index c9cc33881bef..02d57d98ef9b 100644
+--- a/drivers/usb/dwc3/dwc3-haps.c
++++ b/drivers/usb/dwc3/dwc3-haps.c
+@@ -15,10 +15,6 @@
+ #include <linux/platform_device.h>
+ #include <linux/property.h>
+
+-#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd
+-#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI 0xabce
+-#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31 0xabcf
+-
+ /**
+ * struct dwc3_haps - Driver private structure
+ * @dwc3: child dwc3 platform_device
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index 2792bca03088..05705d0b5689 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -2361,6 +2361,9 @@
+ #define PCI_DEVICE_ID_CENATEK_IDE 0x0001
+
+ #define PCI_VENDOR_ID_SYNOPSYS 0x16c3
++#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd
++#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI 0xabce
++#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31 0xabcf
+
+ #define PCI_VENDOR_ID_USR 0x16ec
+
+--
+2.25.1
+
--- /dev/null
+From f49b09bc0f91c37b009cdab559cf739034e81385 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 14 Aug 2018 17:14:30 -0700
+Subject: PCI: Remove unused NFP32xx IDs
+
+From: Jakub Kicinski <jakub.kicinski@netronome.com>
+
+[ Upstream commit 1ccce46c5e8b8a0d2606fb8bb72bff069ffdc3ab ]
+
+Defines for NFP32xx are no longer used anywhere, remove them.
+
+Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/linux/pci_ids.h | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index d157983b84cf..f4e278493f5b 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -2539,8 +2539,6 @@
+ #define PCI_VENDOR_ID_HUAWEI 0x19e5
+
+ #define PCI_VENDOR_ID_NETRONOME 0x19ee
+-#define PCI_DEVICE_ID_NETRONOME_NFP3200 0x3200
+-#define PCI_DEVICE_ID_NETRONOME_NFP3240 0x3240
+ #define PCI_DEVICE_ID_NETRONOME_NFP4000 0x4000
+ #define PCI_DEVICE_ID_NETRONOME_NFP5000 0x5000
+ #define PCI_DEVICE_ID_NETRONOME_NFP6000 0x6000
+--
+2.25.1
+
--- /dev/null
+From fdff9cd574bd5f63870f8d5f9a1128309d6ceed6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 6 Sep 2019 18:36:06 -0500
+Subject: PCI: Unify ACS quirk desired vs provided checking
+
+From: Bjorn Helgaas <bhelgaas@google.com>
+
+[ Upstream commit 7cf2cba43f15c74bac46dc5f0326805d25ef514d ]
+
+Most of the ACS quirks have a similar pattern of:
+
+ acs_flags &= ~( <controls provided by this device> );
+ return acs_flags ? 0 : 1;
+
+Pull this out into a helper function to simplify the quirks slightly. The
+helper function is also a convenient place for comments about what the list
+of ACS controls means. No functional change intended.
+
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
+Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/quirks.c | 67 +++++++++++++++++++++++++++++---------------
+ 1 file changed, 45 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
+index ae62c0b058dd..0704025a2160 100644
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -4263,6 +4263,24 @@ static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
+ quirk_chelsio_T5_disable_root_port_attributes);
+
++/*
++ * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
++ * by a device
++ * @acs_ctrl_req: Bitmask of desired ACS controls
++ * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
++ * the hardware design
++ *
++ * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
++ * in @acs_ctrl_ena, i.e., the device provides all the access controls the
++ * caller desires. Return 0 otherwise.
++ */
++static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
++{
++ if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req)
++ return 1;
++ return 0;
++}
++
+ /*
+ * AMD has indicated that the devices below do not support peer-to-peer
+ * in any system where they are found in the southbridge with an AMD
+@@ -4306,7 +4324,7 @@ static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
+ /* Filter out flags not applicable to multifunction */
+ acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
+
+- return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
++ return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR);
+ #else
+ return -ENODEV;
+ #endif
+@@ -4344,9 +4362,8 @@ static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
+ * hardware implements and enables equivalent ACS functionality for
+ * these flags.
+ */
+- acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+-
+- return acs_flags ? 0 : 1;
++ return pci_acs_ctrl_enabled(acs_flags,
++ PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+ }
+
+ static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
+@@ -4356,9 +4373,8 @@ static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
+ * transactions with others, allowing masking out these bits as if they
+ * were unimplemented in the ACS capability.
+ */
+- acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+-
+- return acs_flags ? 0 : 1;
++ return pci_acs_ctrl_enabled(acs_flags,
++ PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+ }
+
+ /*
+@@ -4410,17 +4426,16 @@ static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
+ return false;
+ }
+
+-#define INTEL_PCH_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
+-
+ static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
+ {
+ if (!pci_quirk_intel_pch_acs_match(dev))
+ return -ENOTTY;
+
+ if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
+- acs_flags &= ~(INTEL_PCH_ACS_FLAGS);
++ return pci_acs_ctrl_enabled(acs_flags,
++ PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+
+- return acs_flags ? 0 : 1;
++ return pci_acs_ctrl_enabled(acs_flags, 0);
+ }
+
+ /*
+@@ -4435,9 +4450,8 @@ static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
+ */
+ static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
+ {
+- acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+-
+- return acs_flags ? 0 : 1;
++ return pci_acs_ctrl_enabled(acs_flags,
++ PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+ }
+
+ /*
+@@ -4520,7 +4534,7 @@ static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
+
+ pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
+
+- return acs_flags & ~ctrl ? 0 : 1;
++ return pci_acs_ctrl_enabled(acs_flags, ctrl);
+ }
+
+ static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
+@@ -4534,10 +4548,9 @@ static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
+ * perform peer-to-peer with other functions, allowing us to mask out
+ * these bits as if they were unimplemented in the ACS capability.
+ */
+- acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
+- PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
+-
+- return acs_flags ? 0 : 1;
++ return pci_acs_ctrl_enabled(acs_flags,
++ PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
++ PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
+ }
+
+ static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags)
+@@ -4562,9 +4575,8 @@ static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
+ * Allow each Root Port to be in a separate IOMMU group by masking
+ * SV/RR/CR/UF bits.
+ */
+- acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+-
+- return acs_flags ? 0 : 1;
++ return pci_acs_ctrl_enabled(acs_flags,
++ PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
+ }
+
+ static const struct pci_dev_acs_enabled {
+@@ -4663,6 +4675,17 @@ static const struct pci_dev_acs_enabled {
+ { 0 }
+ };
+
++/*
++ * pci_dev_specific_acs_enabled - check whether device provides ACS controls
++ * @dev: PCI device
++ * @acs_flags: Bitmask of desired ACS controls
++ *
++ * Returns:
++ * -ENOTTY: No quirk applies to this device; we can't tell whether the
++ * device provides the desired controls
++ * 0: Device does not provide all the desired controls
++ * >0: Device provides all the controls in @acs_flags
++ */
+ int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
+ {
+ const struct pci_dev_acs_enabled *i;
+--
+2.25.1
+
--- /dev/null
+From e0b10d08356812c4a6ddeecb42e6b4d16015c466 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 12 Nov 2019 05:47:53 -0700
+Subject: PCI: vmd: Add device id for VMD device 8086:9A0B
+
+From: Jon Derrick <jonathan.derrick@intel.com>
+
+[ Upstream commit ec11e5c213cc20cac5e8310728b06793448b9f6d ]
+
+This patch adds support for this VMD device which supports the bus
+restriction mode.
+
+Signed-off-by: Jon Derrick <jonathan.derrick@intel.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/controller/vmd.c | 2 ++
+ include/linux/pci_ids.h | 1 +
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c
+index ab36e5ca1aca..b52885020c85 100644
+--- a/drivers/pci/controller/vmd.c
++++ b/drivers/pci/controller/vmd.c
+@@ -866,6 +866,8 @@ static const struct pci_device_id vmd_ids[] = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_28C0),
+ .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW |
+ VMD_FEAT_HAS_BUS_RESTRICTIONS,},
++ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_9A0B),
++ .driver_data = VMD_FEAT_HAS_BUS_RESTRICTIONS,},
+ {0,}
+ };
+ MODULE_DEVICE_TABLE(pci, vmd_ids);
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index b047b0af530d..8d3b39028968 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -3003,6 +3003,7 @@
+ #define PCI_DEVICE_ID_INTEL_84460GX 0x84ea
+ #define PCI_DEVICE_ID_INTEL_IXP4XX 0x8500
+ #define PCI_DEVICE_ID_INTEL_IXP2800 0x9004
++#define PCI_DEVICE_ID_INTEL_VMD_9A0B 0x9a0b
+ #define PCI_DEVICE_ID_INTEL_S21152BB 0xb152
+
+ #define PCI_VENDOR_ID_SCALEMP 0x8686
+--
+2.25.1
+
--- /dev/null
+From 91eee8e052739d9f56c13506df3e2ea4e4ab1347 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 8 May 2020 14:53:40 +0800
+Subject: serial: 8250_pci: Move Pericom IDs to pci_ids.h
+
+From: Kai-Heng Feng <kai.heng.feng@canonical.com>
+
+[ Upstream commit 62a7f3009a460001eb46984395280dd900bc4ef4 ]
+
+Move the IDs to pci_ids.h so it can be used by next patch.
+
+Link: https://lore.kernel.org/r/20200508065343.32751-1-kai.heng.feng@canonical.com
+Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Cc: stable@vger.kernel.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/tty/serial/8250/8250_pci.c | 6 ------
+ include/linux/pci_ids.h | 6 ++++++
+ 2 files changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c
+index bbe5cba21522..02091782bc1e 100644
+--- a/drivers/tty/serial/8250/8250_pci.c
++++ b/drivers/tty/serial/8250/8250_pci.c
+@@ -1690,12 +1690,6 @@ pci_wch_ch38x_setup(struct serial_private *priv,
+ #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
+ #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
+
+-#define PCI_VENDOR_ID_PERICOM 0x12D8
+-#define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
+-#define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
+-#define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
+-#define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
+-
+ #define PCI_VENDOR_ID_ACCESIO 0x494f
+ #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
+ #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index 14baae112a54..c0dd2f749d3f 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -1833,6 +1833,12 @@
+ #define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2
+ #define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018
+
++#define PCI_VENDOR_ID_PERICOM 0x12D8
++#define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
++#define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
++#define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
++#define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
++
+ #define PCI_SUBVENDOR_ID_CHASE_PCIFAST 0x12E0
+ #define PCI_SUBDEVICE_ID_CHASE_PCIFAST4 0x0031
+ #define PCI_SUBDEVICE_ID_CHASE_PCIFAST8 0x0021
+--
+2.25.1
+
ext4-fix-ext_max_extent-index-to-check-for-zeroed-eh_max.patch
ext4-fix-error-pointer-dereference.patch
ext4-fix-race-between-ext4_sync_parent-and-rename.patch
+pci-avoid-pericom-usb-controller-ohci-ehci-pme-defec.patch
+pci-avoid-flr-for-amd-matisse-hd-audio-usb-3.0.patch
+pci-avoid-flr-for-amd-starship-usb-3.0.patch
+pci-add-acs-quirk-for-iproc-paxb.patch
+pci-add-acs-quirk-for-intel-root-complex-integrated-.patch
+pci-remove-unused-nfp32xx-ids.patch
+pci-ipmi-move-ipmi-pci-class-id-defines-to-pci_ids.h.patch
+hwmon-k10temp-x86-amd_nb-consolidate-shared-device-i.patch
+x86-amd_nb-add-pci-device-ids-for-family-17h-model-3.patch
+pci-add-usr-vendor-id-and-use-it-in-r8169-and-w6692-.patch
+pci-move-synopsys-haps-platform-device-ids.patch
+pci-move-rohm-vendor-id-to-generic-list.patch
+misc-pci_endpoint_test-add-the-layerscape-ep-device-.patch
+misc-pci_endpoint_test-add-support-to-test-pci-ep-in.patch
+pci-add-synopsys-endpoint-edda-device-id.patch
+pci-add-nvidia-gpu-multi-function-power-dependencies.patch
+pci-enable-nvidia-hda-controllers.patch
+pci-mediatek-add-controller-support-for-mt7629.patch
+x86-amd_nb-add-pci-device-ids-for-family-17h-model-7.patch
+alsa-lx6464es-add-support-for-lx6464ese-pci-express-.patch
+pci-add-genesys-logic-inc.-vendor-id.patch
+pci-add-amazon-s-annapurna-labs-vendor-id.patch
+pci-vmd-add-device-id-for-vmd-device-8086-9a0b.patch
+x86-amd_nb-add-family-19h-pci-ids.patch
+pci-add-loongson-vendor-id.patch
+serial-8250_pci-move-pericom-ids-to-pci_ids.h.patch
+pci-make-acs-quirk-implementations-more-uniform.patch
+pci-unify-acs-quirk-desired-vs-provided-checking.patch
+pci-generalize-multi-function-power-dependency-devic.patch
--- /dev/null
+From 7d66e158a156c1721645349e8f063d260320567c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 10 Jan 2020 01:56:49 +0000
+Subject: x86/amd_nb: Add Family 19h PCI IDs
+
+From: Yazen Ghannam <yazen.ghannam@amd.com>
+
+[ Upstream commit b3f79ae45904ae987a7c06a9e8d6084d7b73e67f ]
+
+Add the new PCI Device 18h IDs for AMD Family 19h systems. Note that
+Family 19h systems will not have a new PCI root device ID.
+
+Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Link: https://lkml.kernel.org/r/20200110015651.14887-4-Yazen.Ghannam@amd.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/kernel/amd_nb.c | 3 +++
+ include/linux/pci_ids.h | 1 +
+ 2 files changed, 4 insertions(+)
+
+diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
+index be1d15a27079..923b4bac9613 100644
+--- a/arch/x86/kernel/amd_nb.c
++++ b/arch/x86/kernel/amd_nb.c
+@@ -21,6 +21,7 @@
+ #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
+ #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
+ #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
++#define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654
+
+ /* Protect the PCI config register pairs used for SMN and DF indirect access. */
+ static DEFINE_MUTEX(smn_mutex);
+@@ -51,6 +52,7 @@ const struct pci_device_id amd_nb_misc_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
++ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
+ {}
+ };
+ EXPORT_SYMBOL_GPL(amd_nb_misc_ids);
+@@ -65,6 +67,7 @@ static const struct pci_device_id amd_nb_link_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) },
++ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
+ {}
+ };
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index 8d3b39028968..a81fcb2f2cb7 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -549,6 +549,7 @@
+ #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
+ #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F3 0x1493
+ #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F3 0x1443
++#define PCI_DEVICE_ID_AMD_19H_DF_F3 0x1653
+ #define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
+ #define PCI_DEVICE_ID_AMD_LANCE 0x2000
+ #define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
+--
+2.25.1
+
--- /dev/null
+From de16e3dba90dcbded764872ccaffb4ff85c85dae Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 6 Nov 2018 20:08:18 +0000
+Subject: x86/amd_nb: Add PCI device IDs for family 17h, model 30h
+
+From: Woods, Brian <Brian.Woods@amd.com>
+
+[ Upstream commit be3518a16ef270e3b030a6ae96055f83f51bd3dd ]
+
+Add the PCI device IDs for family 17h model 30h, since they are needed
+for accessing various registers via the data fabric/SMN interface.
+
+Signed-off-by: Brian Woods <brian.woods@amd.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+CC: Bjorn Helgaas <bhelgaas@google.com>
+CC: Clemens Ladisch <clemens@ladisch.de>
+CC: Guenter Roeck <linux@roeck-us.net>
+CC: "H. Peter Anvin" <hpa@zytor.com>
+CC: Ingo Molnar <mingo@redhat.com>
+CC: Jean Delvare <jdelvare@suse.com>
+CC: Jia Zhang <qianyue.zj@alibaba-inc.com>
+CC: <linux-hwmon@vger.kernel.org>
+CC: <linux-pci@vger.kernel.org>
+CC: Pu Wen <puwen@hygon.cn>
+CC: Thomas Gleixner <tglx@linutronix.de>
+CC: x86-ml <x86@kernel.org>
+Link: http://lkml.kernel.org/r/20181106200754.60722-4-brian.woods@amd.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/kernel/amd_nb.c | 6 ++++++
+ include/linux/pci_ids.h | 1 +
+ 2 files changed, 7 insertions(+)
+
+diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
+index bf440af5ff9c..b95db8ce83bf 100644
+--- a/arch/x86/kernel/amd_nb.c
++++ b/arch/x86/kernel/amd_nb.c
+@@ -16,8 +16,10 @@
+
+ #define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
+ #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
++#define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480
+ #define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
+ #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
++#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
+
+ /* Protect the PCI config register pairs used for SMN and DF indirect access. */
+ static DEFINE_MUTEX(smn_mutex);
+@@ -27,9 +29,11 @@ static u32 *flush_words;
+ static const struct pci_device_id amd_root_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
++ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
+ {}
+ };
+
++
+ #define PCI_DEVICE_ID_AMD_CNB17H_F4 0x1704
+
+ const struct pci_device_id amd_nb_misc_ids[] = {
+@@ -43,6 +47,7 @@ const struct pci_device_id amd_nb_misc_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
++ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
+ {}
+ };
+@@ -56,6 +61,7 @@ static const struct pci_device_id amd_nb_link_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
++ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
+ {}
+ };
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index 857cfd6281a0..81c7af243a31 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -547,6 +547,7 @@
+ #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F4 0x1584
+ #define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
+ #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
++#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F3 0x1493
+ #define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
+ #define PCI_DEVICE_ID_AMD_LANCE 0x2000
+ #define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
+--
+2.25.1
+
--- /dev/null
+From 4a37b265c37c69e8f6a73acf179b2acdfb4544a9 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 22 Jul 2019 20:45:10 +0300
+Subject: x86/amd_nb: Add PCI device IDs for family 17h, model 70h
+
+From: Marcel Bocu <marcel.p.bocu@gmail.com>
+
+[ Upstream commit af4e1c5eca95bed1192d8dc45c8ed63aea2209e8 ]
+
+The AMD Ryzen gen 3 processors came with a different PCI IDs for the
+function 3 & 4 which are used to access the SMN interface. The root
+PCI address however remained at the same address as the model 30h.
+
+Adding the F3/F4 PCI IDs respectively to the misc and link ids appear
+to be sufficient for k10temp, so let's add them and follow up on the
+patch if other functions need more tweaking.
+
+Vicki Pfau sent an identical patch after I checked that no-one had
+written this patch. I would have been happy about dropping my patch but
+unlike for his patch series, I had already Cc:ed the x86 people and
+they already reviewed the changes. Since Vicki has not answered to
+any email after his initial series, let's assume she is on vacation
+and let's avoid duplication of reviews from the maintainers and merge
+my series. To acknowledge Vicki's anteriority, I added her S-o-b to
+the patch.
+
+v2, suggested by Guenter Roeck and Brian Woods:
+ - rename from 71h to 70h
+
+Signed-off-by: Vicki Pfau <vi@endrift.com>
+Signed-off-by: Marcel Bocu <marcel.p.bocu@gmail.com>
+Tested-by: Marcel Bocu <marcel.p.bocu@gmail.com>
+Acked-by: Thomas Gleixner <tglx@linutronix.de>
+Acked-by: Brian Woods <brian.woods@amd.com>
+Acked-by: Bjorn Helgaas <bhelgaas@google.com> # pci_ids.h
+
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Ingo Molnar <mingo@redhat.com>
+Cc: Borislav Petkov <bp@alien8.de>
+Cc: "H. Peter Anvin" <hpa@zytor.com>
+Cc: x86@kernel.org
+Cc: "Woods, Brian" <Brian.Woods@amd.com>
+Cc: Clemens Ladisch <clemens@ladisch.de>
+Cc: Jean Delvare <jdelvare@suse.com>
+Cc: Guenter Roeck <linux@roeck-us.net>
+Cc: linux-hwmon@vger.kernel.org
+Link: https://lore.kernel.org/r/20190722174510.2179-1-marcel.p.bocu@gmail.com
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/kernel/amd_nb.c | 3 +++
+ include/linux/pci_ids.h | 1 +
+ 2 files changed, 4 insertions(+)
+
+diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
+index b95db8ce83bf..be1d15a27079 100644
+--- a/arch/x86/kernel/amd_nb.c
++++ b/arch/x86/kernel/amd_nb.c
+@@ -20,6 +20,7 @@
+ #define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
+ #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
+ #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
++#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
+
+ /* Protect the PCI config register pairs used for SMN and DF indirect access. */
+ static DEFINE_MUTEX(smn_mutex);
+@@ -49,6 +50,7 @@ const struct pci_device_id amd_nb_misc_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
++ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
+ {}
+ };
+ EXPORT_SYMBOL_GPL(amd_nb_misc_ids);
+@@ -62,6 +64,7 @@ static const struct pci_device_id amd_nb_link_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
++ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
+ {}
+ };
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index a7abaaa9bc27..81ddbd891202 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -548,6 +548,7 @@
+ #define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
+ #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
+ #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F3 0x1493
++#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F3 0x1443
+ #define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
+ #define PCI_DEVICE_ID_AMD_LANCE 0x2000
+ #define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
+--
+2.25.1
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
