arm64/mm: Override PARange for !LPA2 and use it consistently

When FEAT_LPA{,2} are not implemented, the ID_AA64MMFR0_EL1.PARange and
TCR.IPS values corresponding with 52-bit physical addressing are
reserved.

Setting the TCR.IPS field to 0b110 (52-bit physical addressing) has side
effects, such as how the TTBRn_ELx.BADDR fields are interpreted, and so
it is important that disabling FEAT_LPA2 (by overriding the
ID_AA64MMFR0.TGran fields) also presents a PARange field consistent with
that.

So limit the field to 48 bits unless LPA2 is enabled, and update
existing references to use the override consistently.

Fixes: 352b0395b505 ("arm64: Enable 52-bit virtual addressing for 4k and 16k granule configs")
Cc: stable@vger.kernel.org
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20241212081841.2168124-10-ardb+git@google.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index 3d8d534a7a77c22f47818e645ff0ba0698bd6ba4..ad63457a05c5b02e2fdcf18a8fa5069297362822 100644 (file)
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -343,6 +343,11 @@ alternative_cb_end
        // Narrow PARange to fit the PS field in TCR_ELx
        ubfx    \tmp0, \tmp0, #ID_AA64MMFR0_EL1_PARANGE_SHIFT, #3
        mov     \tmp1, #ID_AA64MMFR0_EL1_PARANGE_MAX
+#ifdef CONFIG_ARM64_LPA2
+alternative_if_not ARM64_HAS_VA52
+       mov     \tmp1, #ID_AA64MMFR0_EL1_PARANGE_48
+alternative_else_nop_endif
+#endif
        cmp     \tmp0, \tmp1
        csel    \tmp0, \tmp1, \tmp0, hi
        bfi     \tcr, \tmp0, \pos, #3

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 6ce71f444ed84f9056196bb21bbfac61c9687e30..f8cb8a6ab98a2af526a8a208f479d271d35ad604 100644 (file)
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -3478,7 +3478,7 @@ static void verify_hyp_capabilities(void)
                return;
 
        safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
-       mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
+       mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
        mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
 
        /* Verify VMID bits */

diff --git a/arch/arm64/kernel/pi/idreg-override.c b/arch/arm64/kernel/pi/idreg-override.c
index 22159251eb3a6a5efea90ebda2910ebcfff52b8f..c6b185b885f7002c74230643f03e231ce68d9618 100644 (file)
--- a/arch/arm64/kernel/pi/idreg-override.c
+++ b/arch/arm64/kernel/pi/idreg-override.c
@@ -83,6 +83,15 @@ static bool __init mmfr2_varange_filter(u64 val)
                id_aa64mmfr0_override.val |=
                        (ID_AA64MMFR0_EL1_TGRAN_LPA2 - 1) << ID_AA64MMFR0_EL1_TGRAN_SHIFT;
                id_aa64mmfr0_override.mask |= 0xfU << ID_AA64MMFR0_EL1_TGRAN_SHIFT;
+
+               /*
+                * Override PARange to 48 bits - the override will just be
+                * ignored if the actual PARange is smaller, but this is
+                * unlikely to be the case for LPA2 capable silicon.
+                */
+               id_aa64mmfr0_override.val |=
+                       ID_AA64MMFR0_EL1_PARANGE_48 << ID_AA64MMFR0_EL1_PARANGE_SHIFT;
+               id_aa64mmfr0_override.mask |= 0xfU << ID_AA64MMFR0_EL1_PARANGE_SHIFT;
        }
 #endif
        return true;

diff --git a/arch/arm64/kernel/pi/map_kernel.c b/arch/arm64/kernel/pi/map_kernel.c
index f374a3e5a5fe10b0a0491edaf1a31a7f62602606..e57b043f324b51b7db873daa61b079bfb07244e0 100644 (file)
--- a/arch/arm64/kernel/pi/map_kernel.c
+++ b/arch/arm64/kernel/pi/map_kernel.c
@@ -136,6 +136,12 @@ static void noinline __section(".idmap.text") set_ttbr0_for_lpa2(u64 ttbr)
 {
        u64 sctlr = read_sysreg(sctlr_el1);
        u64 tcr = read_sysreg(tcr_el1) | TCR_DS;
+       u64 mmfr0 = read_sysreg(id_aa64mmfr0_el1);
+       u64 parange = cpuid_feature_extract_unsigned_field(mmfr0,
+                                                          ID_AA64MMFR0_EL1_PARANGE_SHIFT);
+
+       tcr &= ~TCR_IPS_MASK;
+       tcr |= parange << TCR_IPS_SHIFT;
 
        asm("   msr     sctlr_el1, %0           ;"
            "   isb                             ;"

diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index ccdef53872a0bf72f153ff2c9121fe393cd1b24a..9c0b8d9558fc41e3311bdf00936223f56c074f7d 100644 (file)
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -279,7 +279,12 @@ void __init arm64_memblock_init(void)
 
        if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) {
                extern u16 memstart_offset_seed;
-               u64 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
+
+               /*
+                * Use the sanitised version of id_aa64mmfr0_el1 so that linear
+                * map randomization can be enabled by shrinking the IPA space.
+                */
+               u64 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
                int parange = cpuid_feature_extract_unsigned_field(
                                        mmfr0, ID_AA64MMFR0_EL1_PARANGE_SHIFT);
                s64 range = linear_region_size -