soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data

There are different software reset registers for difference MTK SoCs.
Therefore, we add a new variable "sw0_rst_offset" to control it.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220217082626.15728-2-rex-bc.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 9dee485807c9400225a063dfbb6ae14f619c12a4..0c021f4b76d2149fbeabf755e11938d4e12f5ac4 100644 (file)
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -25,6 +25,8 @@
 #define MT8183_RDMA0_SOUT_COLOR0               0x1
 #define MT8183_RDMA1_SOUT_DSI0                 0x1
 
+#define MT8183_MMSYS_SW0_RST_B                 0x140
+
 static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
        {
                DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,

diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 50c797d70ddd7be00a4f1a71eac03b370c99eb83..4fc4c2c9ea20db4dfc9956ebf6ee172abf7961ef 100644 (file)
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -49,12 +49,14 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
        .clk_driver = "clk-mt8173-mm",
        .routes = mmsys_default_routing_table,
        .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
+       .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
 };
 
 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
        .clk_driver = "clk-mt8183-mm",
        .routes = mmsys_mt8183_routing_table,
        .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
+       .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
 };
 
 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
@@ -129,14 +131,14 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
 
        spin_lock_irqsave(&mmsys->lock, flags);
 
-       reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B);
+       reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
 
        if (assert)
                reg &= ~BIT(id);
        else
                reg |= BIT(id);
 
-       writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B);
+       writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
 
        spin_unlock_irqrestore(&mmsys->lock, flags);
 

diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 8b0ed05117ea401089a3745363a9193d6e6b4bdf..77f37f8c715bcfc396dddc9511b01d9cdff137af 100644 (file)
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -78,8 +78,6 @@
 #define DSI_SEL_IN_RDMA                                0x1
 #define DSI_SEL_IN_MASK                                0x1
 
-#define MMSYS_SW0_RST_B                                0x140
-
 struct mtk_mmsys_routes {
        u32 from_comp;
        u32 to_comp;
@@ -92,6 +90,7 @@ struct mtk_mmsys_driver_data {
        const char *clk_driver;
        const struct mtk_mmsys_routes *routes;
        const unsigned int num_routes;
+       const u16 sw0_rst_offset;
 };
 
 /*