testsuite: RISC-V: Skip V and Zvbb tests for ILP32E/ILP64E ABIs

Some tests add options for V and Zvbb extensions, but those extensions
are not compatible with the E ABI variants.  This leads to spurious test
failures when toolchain's default ABI is ILP32E or ILP64E:

  spawn ... -march=rv32ecv_zvbb ...
  cc1: error: ILP32E ABI does not support the 'D' extension
  cc1: sorry, unimplemented: Currently the 'V' implementation requires the 'M' extension

Fix by skipping the tests when toolchain's default ABI is E variant.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vandn-1.c: Skip if default
	is E ABI.
	* gcc.target/riscv/rvv/autovec/binop/vrolr-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vwsll-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vwsll-template.h: Ditto.
	* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/clz-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/ctz-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/popcount-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/popcount-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/popcount-3.c: Ditto.
	* gcc.target/riscv/rvv/base/cmpmem-1.c: Ditto.
	* gcc.target/riscv/rvv/base/cmpmem-3.c: Ditto.
	* gcc.target/riscv/rvv/base/cmpmem-4.c: Ditto.
	* gcc.target/riscv/rvv/base/cpymem-1.c: Ditto.
	* gcc.target/riscv/rvv/base/cpymem-2.c: Ditto.
	* gcc.target/riscv/rvv/base/cpymem-3.c: Ditto.
	* gcc.target/riscv/rvv/base/movmem-1.c: Ditto.
	* gcc.target/riscv/rvv/base/pr115068.c: Ditto.
	* gcc.target/riscv/rvv/base/setmem-1.c: Ditto.
	* gcc.target/riscv/rvv/base/setmem-2.c: Ditto.
	* gcc.target/riscv/rvv/base/setmem-3.c: Ditto.
	* gcc.target/riscv/rvv/base/vwaddsub-1.c: Ditto.

Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c
index 3bb5bf8dd5ba7c01a494fba98dd9414da0b3d380..dfdc64b568dc2b9a708fa2f491a4663a034ad8a5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvbb" } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c
index 55dac27697cb2ce226f6f23d187bf4874aa8f028..1c5f6e046d025b24827cfe68f558887357adfd4b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvbb" } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c
index a2e5b4f5aa1223cac3d1b9ebe49d3f4ff5737485..0a67db77a6aef04e3247537e9a5d334fde589cce 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvbb" } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h
index 376cbaee0d51d659dc620f640d065c34216e15d0..89b7624fe9fe8376eb6111095673b109db524234 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvbb" } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c
index 1fd3644886ac0f6865c8c8d30128e1fd6edaa706..de5a5ed7d56a9f3a25078d1a60dd2d215fe34afe 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvbb" } */
 /* { dg-additional-options "-fno-vect-cost-model -fdump-tree-vect-details -mrvv-max-lmul=m4" } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c
index c27d9d399b935d384227c2d20e61e96a68ce4c35..483b58f8af70031ccc3f5188ab601c4773b2274e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvbb" } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c
index d5989bd5aad5adc03967a1a41c3a49eaba12be05..2425dc86404a671a446ffb9b6dc519d8f58dae80 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvbb" } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
index 1396e46ec8cc13eea7fcd615153d75577bd83443..12324f19867a4064cbf03f1b430f4360731e3603 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
index 116cc304da37d61746238090a6bb5c18155f208b..7e6880370e137283e728db0791f351894b6559b5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-slp-details" } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c
index 00b87a07fd89080e2535dde26a34c0a04c013e51..6bf8909988432c3c890c81fa8b55f7d4a0894b91 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvbb" } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c
index 6bc8b07bc2c6b30b17b1e67fb2ecd370eecde49a..9edd6cb54ba93ef07fe09767b80260e997e2eef6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-add-options riscv_v } */
 /* { dg-additional-options "-O3 -mrvv-max-lmul=dynamic" } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c
index 5ca31af90fb77888fc96fc400209e8bf3b6b78ee..82aa307657929b612d0a20d0273a74693c21fe02 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-add-options riscv_v } */
 /* { dg-additional-options "-O3 -mrvv-max-lmul=m1" } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c
index 5860b27a2335be9c0b39894e832d61b473ad1c72..e2dd6a1c45fe2c2e4757ee222ef856e7ad786ec8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-add-options riscv_v } */
 /* { dg-additional-options "-O3 -mrvv-max-lmul=m8" } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
index 81d14d83633420fa51f5c0ff576a79999da70d0c..654c80087d247ad59664df9c8cef22adc8855046 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-add-options riscv_v } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
index 7b6a429f34cf4b32264009eccaf8a87c73d9205b..3d79b5987fd82bd36c46daf1be703c6683be646e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 /* { dg-add-options riscv_v } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c
index f07078ba6a7c8e4fea5533664ab62958f4283de3..2b75b314fae7801e359e44a2a394d3868d755e1f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 /* { dg-add-options riscv_v } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c
index 1f148bc70528ccbb15103b3f6a6e9722c44ec2fe..03e633be2719616e4cd6e8b86b7c2bdc4edeee37 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-add-options riscv_v } */
 /* { dg-additional-options "-O3 -mrvv-max-lmul=dynamic" } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
index 8359e81629d8df4bac5d6339ea2f61ca42b3f2ee..af2cba6039d6283cd39846c4938d02540dac02d1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-add-options riscv_v } */
 /* { dg-additional-options "-std=gnu99" } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c
index 22844ff348ccd1e5cb6a8ab2ecafe9f1a4b7d130..a22d366de9b06d7bf1fdc32564c9906dc98482a2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-add-options riscv_v } */
 /* { dg-additional-options "-O3 -mrvv-max-lmul=dynamic" } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c
index 838fbebadff34208ed4d62dccb333c8efc37e23e..a10886862b286c5a259af6e9b696adada9cbe695 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-add-options riscv_v } */
 /* { dg-additional-options "-O3 -mrvv-max-lmul=m1" } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c
index 449338197158dabf8c96642a915e9260cb65d798..460a8f2c7fe9d27be795d30ed55124023eef9182 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-add-options riscv_v } */
 /* { dg-additional-options "-O3 -mrvv-max-lmul=m8" } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
index 196215a1f7b78caadb4081f285df06d6a6957f8b..6e027a555f37741bd1401c1be97bd81086c0f6f0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-add-options riscv_v } */
 /* { dg-additional-options "-std=gnu99 -O3 -fno-schedule-insns -fno-schedule-insns2" } */