dpll: zl3073x: add ref sync and output clock type helpers

Add ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR and ZL_REF_SYNC_CTRL_PAIR
register definitions.

Add inline helpers to get and set the sync control mode and sync pair
fields of the reference sync control register:

  zl3073x_ref_sync_mode_get/set() - ZL_REF_SYNC_CTRL_MODE field
  zl3073x_ref_sync_pair_get/set() - ZL_REF_SYNC_CTRL_PAIR field

Add inline helpers to get and set the clock type field of the output
mode register:

  zl3073x_out_clock_type_get/set() - ZL_OUTPUT_MODE_CLOCK_TYPE field

Convert existing esync callbacks to use the new helpers.

Reviewed-by: Petr Oros <poros@redhat.com>
Reviewed-by: Prathosh Satish <Prathosh.Satish@microchip.com>
Signed-off-by: Ivan Vecera <ivecera@redhat.com>
Link: https://patch.msgid.link/20260408102716.443099-4-ivecera@redhat.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/dpll/zl3073x/dpll.c b/drivers/dpll/zl3073x/dpll.c
index 445f4bccb9aabb1a5cbc0ab517d8386c365f5540..dc649cf103cb4564a7fc681d1d06f4b02f5451c1 100644 (file)
--- a/drivers/dpll/zl3073x/dpll.c
+++ b/drivers/dpll/zl3073x/dpll.c
@@ -139,7 +139,7 @@ zl3073x_dpll_input_pin_esync_get(const struct dpll_pin *dpll_pin,
        esync->range = esync_freq_ranges;
        esync->range_num = ARRAY_SIZE(esync_freq_ranges);
 
-       switch (FIELD_GET(ZL_REF_SYNC_CTRL_MODE, ref->sync_ctrl)) {
+       switch (zl3073x_ref_sync_mode_get(ref)) {
        case ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75:
                esync->freq = ref->esync_n_div == ZL_REF_ESYNC_DIV_1HZ ? 1 : 0;
                esync->pulse = 25;
@@ -175,8 +175,7 @@ zl3073x_dpll_input_pin_esync_set(const struct dpll_pin *dpll_pin,
        else
                sync_mode = ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75;
 
-       ref.sync_ctrl &= ~ZL_REF_SYNC_CTRL_MODE;
-       ref.sync_ctrl |= FIELD_PREP(ZL_REF_SYNC_CTRL_MODE, sync_mode);
+       zl3073x_ref_sync_mode_set(&ref, sync_mode);
 
        if (freq) {
                /* 1 Hz is only supported frequency now */
@@ -595,7 +594,7 @@ zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin,
        const struct zl3073x_synth *synth;
        const struct zl3073x_out *out;
        u32 synth_freq, out_freq;
-       u8 clock_type, out_id;
+       u8 out_id;
 
        out_id = zl3073x_output_pin_out_get(pin->id);
        out = zl3073x_out_state_get(zldev, out_id);
@@ -618,8 +617,7 @@ zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin,
        esync->range = esync_freq_ranges;
        esync->range_num = ARRAY_SIZE(esync_freq_ranges);
 
-       clock_type = FIELD_GET(ZL_OUTPUT_MODE_CLOCK_TYPE, out->mode);
-       if (clock_type != ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC) {
+       if (zl3073x_out_clock_type_get(out) != ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC) {
                /* No need to read esync data if it is not enabled */
                esync->freq = 0;
                esync->pulse = 0;
@@ -652,8 +650,8 @@ zl3073x_dpll_output_pin_esync_set(const struct dpll_pin *dpll_pin,
        struct zl3073x_dpll_pin *pin = pin_priv;
        const struct zl3073x_synth *synth;
        struct zl3073x_out out;
-       u8 clock_type, out_id;
        u32 synth_freq;
+       u8 out_id;
 
        out_id = zl3073x_output_pin_out_get(pin->id);
        out = *zl3073x_out_state_get(zldev, out_id);
@@ -665,15 +663,13 @@ zl3073x_dpll_output_pin_esync_set(const struct dpll_pin *dpll_pin,
        if (zl3073x_out_is_ndiv(&out))
                return -EOPNOTSUPP;
 
-       /* Select clock type */
+       /* Update clock type in output mode */
        if (freq)
-               clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC;
+               zl3073x_out_clock_type_set(&out,
+                                          ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC);
        else
-               clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL;
-
-       /* Update clock type in output mode */
-       out.mode &= ~ZL_OUTPUT_MODE_CLOCK_TYPE;
-       out.mode |= FIELD_PREP(ZL_OUTPUT_MODE_CLOCK_TYPE, clock_type);
+               zl3073x_out_clock_type_set(&out,
+                                          ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL);
 
        /* If esync is being disabled just write mailbox and finish */
        if (!freq)

diff --git a/drivers/dpll/zl3073x/out.h b/drivers/dpll/zl3073x/out.h
index edf40432bba5f072958a5912965dfec3c83fa189..660889c57bffab4efd939c2b84c7a7a2df5b1bfe 100644 (file)
--- a/drivers/dpll/zl3073x/out.h
+++ b/drivers/dpll/zl3073x/out.h
@@ -42,6 +42,28 @@ const struct zl3073x_out *zl3073x_out_state_get(struct zl3073x_dev *zldev,
 int zl3073x_out_state_set(struct zl3073x_dev *zldev, u8 index,
                          const struct zl3073x_out *out);
 
+/**
+ * zl3073x_out_clock_type_get - get output clock type
+ * @out: pointer to out state
+ *
+ * Return: clock type of given output (ZL_OUTPUT_MODE_CLOCK_TYPE_*)
+ */
+static inline u8 zl3073x_out_clock_type_get(const struct zl3073x_out *out)
+{
+       return FIELD_GET(ZL_OUTPUT_MODE_CLOCK_TYPE, out->mode);
+}
+
+/**
+ * zl3073x_out_clock_type_set - set output clock type
+ * @out: pointer to out state
+ * @type: clock type (ZL_OUTPUT_MODE_CLOCK_TYPE_*)
+ */
+static inline void
+zl3073x_out_clock_type_set(struct zl3073x_out *out, u8 type)
+{
+       FIELD_MODIFY(ZL_OUTPUT_MODE_CLOCK_TYPE, &out->mode, type);
+}
+
 /**
  * zl3073x_out_signal_format_get - get output signal format
  * @out: pointer to out state

diff --git a/drivers/dpll/zl3073x/ref.h b/drivers/dpll/zl3073x/ref.h
index be16be20dbc7ebde3f3948fd566d939d10dfbf66..55e80e4f08734c6213ec41aa9e7c48fba937ba6e 100644 (file)
--- a/drivers/dpll/zl3073x/ref.h
+++ b/drivers/dpll/zl3073x/ref.h
@@ -120,6 +120,52 @@ zl3073x_ref_freq_set(struct zl3073x_ref *ref, u32 freq)
        return 0;
 }
 
+/**
+ * zl3073x_ref_sync_mode_get - get sync control mode
+ * @ref: pointer to ref state
+ *
+ * Return: sync control mode (ZL_REF_SYNC_CTRL_MODE_*)
+ */
+static inline u8
+zl3073x_ref_sync_mode_get(const struct zl3073x_ref *ref)
+{
+       return FIELD_GET(ZL_REF_SYNC_CTRL_MODE, ref->sync_ctrl);
+}
+
+/**
+ * zl3073x_ref_sync_mode_set - set sync control mode
+ * @ref: pointer to ref state
+ * @mode: sync control mode (ZL_REF_SYNC_CTRL_MODE_*)
+ */
+static inline void
+zl3073x_ref_sync_mode_set(struct zl3073x_ref *ref, u8 mode)
+{
+       FIELD_MODIFY(ZL_REF_SYNC_CTRL_MODE, &ref->sync_ctrl, mode);
+}
+
+/**
+ * zl3073x_ref_sync_pair_get - get sync pair reference index
+ * @ref: pointer to ref state
+ *
+ * Return: paired reference index
+ */
+static inline u8
+zl3073x_ref_sync_pair_get(const struct zl3073x_ref *ref)
+{
+       return FIELD_GET(ZL_REF_SYNC_CTRL_PAIR, ref->sync_ctrl);
+}
+
+/**
+ * zl3073x_ref_sync_pair_set - set sync pair reference index
+ * @ref: pointer to ref state
+ * @pair: paired reference index
+ */
+static inline void
+zl3073x_ref_sync_pair_set(struct zl3073x_ref *ref, u8 pair)
+{
+       FIELD_MODIFY(ZL_REF_SYNC_CTRL_PAIR, &ref->sync_ctrl, pair);
+}
+
 /**
  * zl3073x_ref_is_diff - check if the given input reference is differential
  * @ref: pointer to ref state

diff --git a/drivers/dpll/zl3073x/regs.h b/drivers/dpll/zl3073x/regs.h
index 5ae50cb761a972f24b32a93a1ee5c3c64ed9085a..d425dc67250fefee49fc3b2c6868dea93c9b377e 100644 (file)
--- a/drivers/dpll/zl3073x/regs.h
+++ b/drivers/dpll/zl3073x/regs.h
@@ -213,7 +213,9 @@
 #define ZL_REG_REF_SYNC_CTRL                   ZL_REG(10, 0x2e, 1)
 #define ZL_REF_SYNC_CTRL_MODE                  GENMASK(2, 0)
 #define ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF 0
+#define ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR     1
 #define ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75        2
+#define ZL_REF_SYNC_CTRL_PAIR                  GENMASK(7, 4)
 
 #define ZL_REG_REF_ESYNC_DIV                   ZL_REG(10, 0x30, 4)
 #define ZL_REF_ESYNC_DIV_1HZ                   0